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204 R. Plyaskin and A. Herkersdorf and program counter values obtained during the cycle accurate simulation. The start and end positions of the groups are denoted using START F and STOP F primitives. In the final step of the trace generation, each primitive type is encoded using a unique identifier. Afterwards, the primitives are stored in a file in the binary form, thus, reducing the size of the generated trace. 3.2 Trace Simulator During the trace simulation which is similar to [15], the black-box CPU models execute primitives of the trace files. The simulation time is advanced according to the processing latencies given in the delay primitives. The absolute SystemC time interval which the CPU model waits is calculated as the annotated number of cycles multiplied with the value of the clock frequency of that CPU component. On execution of read or write primitives, the CPU performs a request to the cache component. Given a memory address tagged to the primitive, the cache model indicates either a hit or a miss for the current transaction. In case of a cache miss, the CPU issues a blocking TLM transaction on the shared arbitrated bus. The cache model used in the trace simulator is highly configurable. The user can configure cache associativity as well as various replacement policies. In contrast to computational latencies that are statically defined by the delay primitives, communication latencies are obtained dynamically at simulation runtime, depending on how shared resources, e.g. on-chip interconnect, are utilized by other CPUs. Please note that neither read nor write primitives are annotated with the data that has to be transferred. Since the functionality of the memory module is abstracted to access latencies only, the actual data written or read from the memory is not required. On execution of START F primitives, the trace simulator starts accumulating the execution time of the annotated subroutine until a STOP F primitive is reached. This information is used later for generation of the profiling results. In addition to the profiling capabilities, the trace simulator is able to measure the utilization of each SoC component. In order to do so, the simulator accumulates the busy time of the respective component. At the end of the simulation, the utilization is calculated as a ratio between the overall busy time and the total simulated time. 3.3 Trace Modification Abstracted representation of the target application using traces allows rapid changes of the workload generated by a CPU. Using a simple text processing tool, the application trace can be modified in an arbitrary way, thus, enabling faster design exploration cycles. Particularly, this could be useful when the designer wants to repartition the functionality between CPUs and HW accelerators and evaluate the resulting impact on the application performance. Since the trace simulation does not require transfers of functional data, the user can create an
A Method for Accurate High-Level Performance Evaluation 205 Fig. 4. Trace primitives for accessing a hardware accelerator abstracted model of the desired HW accelerator, which on request will simulate certain functionality. Functional repartitioning can be performed by a substitution of certain parts of the trace by new patterns for accessing the accelerator component. For this purpose, we have introduced new trace primitives shown in Fig. 4. A WRITE HW primitive represents a transfer of input data to the accelerator denoted by dev id. Upon reception of the data, the hardware accelerator simulates internal processing by waiting for a certain amount of time configured by the user. On execution of a READ HW primitive, the CPU constantly polls the accelerator until the processed data becomes available, and continues executing next trace primitives after the successful read operation. The amount of data that should be written to or read from the accelerator is specified by n bytes parameter. Although the functional data is not transferred to the accelerator, the designer can still investigate the impact of associated communication latencies on the application’s performance. In our framework, the abstracted model of the accelerator was designed in a way in which the component gets locked for a certain CPU during data processing. Therefore, in MPSoC architectures other CPUs will be stalled on a simultaneous access to the component. Please note that the designer can specify more complex access patterns, depending on the type of the hardware accelerator. The processing latency of the HW accelerator can be annotated from the data specifications if the peripheral’s implementation is already available. As an alternative, the proposed methodology can be used for setting the requirements for a not yet existing accelerator. In both cases, the designer is assisted in finding the optimal trade-off between the accelerated execution of the function and the additional load on the on-chip communication infrastructure. 4 Experimental Results In this section, we estimate accuracy of our trace generation method and demonstrate the proposed workflow for evaluation of alternative MPSoC architectures using traces. In the following experiments, cycle accurate simulations were performed in COMeT tool developed by VaST Systems [14]. The tool provides a library of cycle-accurate CPU models that are widely used in industry, as well as models of on-chip buses, memories and other components. Thus, the designer can create a complete model of a system-on-chip which is capable of executing the target binary code.
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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