Architecture of Computing Systems (Lecture Notes in Computer ...

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48 P. Bellasi, W. Fornaciari, and D. Siorpaes References 1. Keating, M., Flynn, D., Aitken, R., Gibbons, A., Shi, K.: Low Power Methodology Manual: For System-on-Chip Design. Springer Publishing Company, Incorporated, Heidelberg (2007) 2. Venkatachalam, V., Franz, M.: Power reduction techniques for microprocessor systems. ACM Comput. Surv. 37(3), 195–237 (2005) 3. Pedram, M.: Power optimization and management in embedded systems. In: ASP- DAC 2001: Proceedings of the 2001 Asia and South Pacific Design Automation Conference, pp. 239–244. ACM, New York (2001) 4. Lorch, J.R., Smith, A.J.: Operating system modifications for task-based speed and voltage. In: MobiSys 2003: Proceedings of the 1st international conference on Mobile systems, applications and services, pp. 215–229. ACM, New York (2003) 5. Pettis, N., Lu, Y.H.: A homogeneous architecture for power policy integration in operating systems. IEEE Transactions on Computers 58(7), 945–955 (2009) 6. Zeng, H., Ellis, C.S., Lebeck, A.R., Vahdat, A.: Ecosystem: managing energy as a first class operating system resource. SIGPLAN Not. 37(10), 123–132 (2002) 7. Anand, M., Nightingale, E.B., Flinn, J.: Ghosts in the machine: interfaces for better power management. In: MobiSys 2004: Proceedings of the 2nd international conference on Mobile systems, applications, and services, pp. 23–35. ACM, New York (2004) 8. Tamai, M., Sun, T., Yasumoto, K., Shibata, N., Ito, M.: Energy-aware video streaming with qos control for portable computing devices. In: NOSSDAV 2004: Proceedings of the 14th international workshop on Network and operating systems support for digital audio and video, pp. 68–73. ACM, New York (2004) 9. Flinn, J., Satyanarayanan, M.: Energy-aware adaptation for mobile applications. In: SOSP 1999: Proceedings of the seventeenth ACM symposium on Operating systems principles, pp. 48–63. ACM, New York (1999) 10. Liu, X., Shenoy, P., Corner, M.D.: Chameleon: Application-level power management. IEEE Transactions on Mobile Computing 7(8), 995–1010 (2008) 11. Yuan, W., Nahrstedt, K.: Energy-efficient soft real-time cpu scheduling for mobile multimedia systems. In: SOSP 2003: Proceedings of the nineteenth ACM symposium on Operating systems principles, pp. 149–163. ACM, New York (2003) 12. Fei, Y., Zhong, L., Jha, N.K.: An energy-aware framework for dynamic software management in mobile computing systems. ACM Trans. Embed. Comput. Syst. 7(3), 1–31 (2008) 13. Snowdon, D.C., Sueur, E.L., Petters, S.M., Heiser, G.: Koala: a platform for oslevel power management. In: EuroSys 2009: Proceedings of the 4th ACM European conference on Computer systems, pp. 289–302. ACM, New York (2009) 14. Brock, B., Rajamani, K.: Dynamic power management for embedded systems. In: Proceedings on IEEE International SoC Conference, September 2003, pp. 416–419 (2003)
Autonomic Workload Management for Multi-core Processor Systems Johannes Zeppenfeld and Andreas Herkersdorf Technische Universität München {zeppenfe,herkersdorf}@tum.de Abstract. This paper presents the use of decentralized self-organization concepts for the efficient dynamic parameterization of hardware components and the autonomic distribution of tasks in a symmetrical multi-core processor system. Using results obtained with an autonomic system on chip simulation model, we show that Learning Classifier Tables, a simplified XCS-based reinforcement learning technique optimized for a low-overhead hardware implementation and integration, achieves nearly optimal results for dynamic workload balancing during run time for a standard networking application at task level. Further investigations show the quantitative differences in optimization quality between scenarios when local and global system information is included in the classifier rules. Autonomic workload management or task repartitioning at run time relieves the software application developers from exploring this NPhard problem during design time, and is able to react to dynamic changes in the MP-SoC operating environment. 1 Introduction 1.1 Multi-core Processing Single-chip multi-processors became the mainstream architecture template for advanced microprocessor designs across a wide spectrum of application domains. Intel, the market leader for general purpose computing, abandoned its traditional strategy to primarily scale microprocessor performance through continued increase in core clock frequency and introduced parallel dual-, quad- and recently octal-core (Nehalem) Xeon processors [1] instead. In their research labs, Intel integrated the 80 core Tera- Scale processor [2] with a 2D network on chip and sophisticated 3D memory stack access. SUN Niagara, ARM MPCore, IBM Cell Broadband Engine, Nvidia GeForce, the CSX700 from ClearSpeed, and the TILE64 from Tilera are other examples of a non-exhaustive list of massively parallel multi-core architectures for use in mobile communications, graphics processing, gaming, industrial automation and highperformance scientific computing. While progress in deep sub-micron CMOS technology integration enabled the physical realization of this vast amount of nominal processing capacity on a single chip, the application programmer community – across all of the above mentioned systems – is minimally supported by tools and methods to efficiently exploit the available parallel resources [3]. We regard this circumstance a major challenge for a fast and efficient adoption of multi-core processors. C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 49–60, 2010. © Springer-Verlag Berlin Heidelberg 2010
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Abdullah, Tariq 174 Alima, Luc Onan
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