Architecture of Computing Systems (Lecture Notes in Computer ...

% of unused pipeline cycles
100
80
60
40
20
0
branch membusy
memfix
pipeline
data latency 0
How to Enhance a Superscalar Processor 11
fetch
data latency 1
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
priority
data latency 2
Fig. 4. Reason why a thread cannot issue an instruction, depending on its priority
Even with minimum latencies (0/0), more than 80% of unused cycles are
due to memory delays (fetch or memfix). Not surprisingly the percentage is
increased when the latencies are increased. Each additional cycle of instruction
memory latency increases the percentage of fetch stalls by 8%, therefore a fast
instruction connection (via scratchpad or instruction cache) is inevitable.
The bars marked with plus show additional membusy latencies. These appear,
when the HPT is executed together with other threads (for the bars without
a plus, the HPT was executed without concurrent threads). If a lower priority
memory access takes multiple cycles and begins in the cycle preceding the cycle
when a HPT memory access should start, the former occupies the memory
controller for multiple cycles and therefore delays the HPT thread.
This effect violates the complete isolation (and thus the hard real-time capability
of the HPT), but it can be avoided by either modifying the WCET
analysis and assuming twice the memory latency or the lower priority memory
accesses can be delayed when a HPT memory access is on the way through the
pipeline (then the distribution of reasons is the same as in the corresponding
case without the plus).
ThelatertechniqueiscalledDominant Memory Access Announcing (DMAA):
when a memory access of the HPT is recognized at the beginning of the pipeline,
it is announced immediately to the memory controller that consequently delays
all memory accesses until the HPT memory access arrives and can be invoked.
Therefore all memory accesses between issue stage and memory controller are
delayed and if the distance between them is longer than the memory latency,
the HPT is never influenced by lower priority memory accesses (for details
see [3]).
Applying the DMAA technique, Fig. 4 shows the average distribution of stall
reasons against the priority. The fixed latencies (which dominate the stall reasons
of the HPT) are less important for lower priority threads. For these threads,
the influence of fetch and pipeline conflicts grows significantly. If the memory
latency is more than zero (rightmost group of Fig. 4), this stall reason dominates
for lower priority threads.