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208 R. Plyaskin and A. Herkersdorf Fig. 5. MPSoC architecture modeled in the trace simulator before and after repartitioning dct function by WRITE HW and READ HW primitives configured with value 64. On execution of WRITE HW, the CPU was trying to access the component by polling its status. If the peripheral was idle, the CPU performed 16 write transactions on the 32-bit bus. After the processing latency assigned to the accelerator had expired, the CPU performed 16 read transactions representing the transfer of the processed data, and the accelerator became available for other CPU components. In [1], L. V. Agostini et al. demonstrated an FPGA implementation of the DCT algorithm and obtained the processing time of an 8×8 pixelblock(5.6µs). We took this value as a reference and annotated the equivalent processing latency to the abstracted accelerator (560 cycles). The latency parameter is configurable and can be changed if other HW implementations have to be considered. The simulation results of the new MPSoC architecture with the DCT accelerator are given in Table 3. Table 2. Profiling results of jpeg application on a 4-CPU architecture in the trace simulator Subroutine Executed cycles Share of total execution time, % CPU0 CPU1 CPU2 CPU3 CPU0 CPU1 CPU2 CPU3 dct 2,278,193 2,277,795 2,277,716 2,277,917 28.1 29.4 28.2 28.1 WriteRawBits16 1,339,100 1,326,305 1,333,059 1,345,854 16.5 17.1 16.5 16.6 EncodeDataUnit 842,872 839,441 841,284 845,318 10.4 10.8 10.4 10.4 zzq encode 817,885 819,343 816,977 818,143 10.1 10.6 10.1 10.1 get MB 475,130 475,671 474,828 475,123 5.9 6.1 5.9 5.9 RGB2YCrCb 438,654 438,916 438,539 439,052 5.4 5.7 5.4 5.4 ... ... ... ... ... ... ... ... ...
A Method for Accurate High-Level Performance Evaluation 209 Table 3. Comparison of execution time of jpeg application on a 4-CPU architecture with and without the DCT accelerator Execution time, cycles CPU instance dct function (average) jpeg application (total) w/o DCT-HW with DCT-HW w/o DCT-HW with DCT-HW CPU0 5,910 668 8,098,417 6,107,352 CPU1 5,909 653 7,752,352 5,755,998 CPU2 5,909 656 8,091,063 6,091,775 CPU3 5,909 657 8,109,849 6,115,119 Due to the additional data transfers to the hardware accelerator and simultaneous use of the component by multiple CPUs, dct function took approximately 1.2 times more than the annotated processing time of the accelerator. Nevertheless, the overall application’s performance was increased by a factor of 1.3 compared to the architecture without the DCT accelerator. 5 Conclusions In this paper, an approach for MPSoC performance estimation was presented in which two domains of cycle accurate and trace-based simulations are combined. For this purpose, we developed a tool that automatically generates a trace file from a CPU cycle accurate simulation at the instruction level. We showed that the trace simulation allows achieving better simulation performance with a marginal loss of accuracy compared to the reference CPU simulator. We further demonstrated how a trace can be applied during high-level design space explorations, particularly for the analysis of functional repartitioning between CPUs and HW accelerators in an MPSoC. Our approach can be also applied for trace generation using RTL processor models. This would allow achieving better accuracy of the traces and even higher simulation speed up comparing to the instruction set simulators. There are some problems that have to be solved in the presented method. Currently, an instruction cache is not considered during the trace generation. It is also assumed that there are no data dependencies between the traces running on a MPSoC architecture. In our future work, in addition to overcoming these problems we are planning to add inter-trace synchronization to our trace simulator, and extend the framework for modeling complex multi-tasking applications running under control of a real-time operating system. Acknowledgments. We would like to thank J. Zeppenfeld and H. Rauchfuss for their help on the trace-based SystemC TLM simulator, as well as Z. Wang for his suggestions for the improvement of simulation performance. We also would like to express our gratitude to the VaST Academic Program for providing us with CoMET tool, BMW and Bosch for supporting our work, as well as to many reviewers for their valuable comments.
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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130 M. Kayaalp et al. INSTRUCTION 1
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