Architecture of Computing Systems (Lecture Notes in Computer ...

Efficient Transaction Nesting in Hardware Transactional Memory 145
Table 1. ISA Extensions and Programming Interface
Instruction Description Programming interface
XB transaction start BEGIN TRANSACTION()
XC transaction end COMMIT TRANSACTION()
Table 2. Configuration of Target System
Item Configuration
cache size L1: 64KB+64KB L2: 16MB
transactional buffer: 64KB
cache line size 64 bytes
cache coherence protocol MESI CMP filter directory
interconnection network hierachical switch topology
5 Evaluation and Analysis
5.1 Experimental Environment
The CPR scheme and system are evaluated on a simulation platform which is
based on the full-system simulator Virtutech Simics [17] and GEMS [18]. By
execution-driven simulating, the operating system and applications can be run
on the platform.
The transactional memory system proposed in this paper is implemented by
extending the simulator. The target system is based on Sparc processor with the
extensions of hardware components and instruction set for transaction memory.
The number of processor cores varies from 2 to 16. And the operating system is
Solaris. Table 2 shows configurations of the target system.
The target system is evaluated using seven micro-benchmark applications as
listed in Table 3. These applications fall into two categories: share-h, share-m
and share-n have the same number of nesting levels but different densities of data
sharing among nesting levels; nest-1 to nest-4 have different number of nesting
levels but no data sharing among nesting levels.
Each application is executed in transactional memory with the support of
CPR scheme and original flattening model, and performance data is obtained at
the same time.
Table 3. Micro-benchmark Applications
Program name Number of nesting level Data sharing among nesting levels
share-h 4 high
share-m 4 middle
share-n 4 none
nest1-nest4 1, 2, 3, 4 none