Architecture of Computing Systems (Lecture Notes in Computer ...

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58 J. Zeppenfeld and A. Herkersdorf Objective Value Avg. Frequency (MHz) 20% 15% 10% 5% 0% 140 120 100 80 60 40 20 0 0 s 0 s 4 ms 4 ms 8 ms 8 ms 12 ms 12 ms 16 ms 16 ms 20 ms 20 ms 24 ms 24 ms 28 ms 28 ms DVFS Pipe DVFS R2C Auto Global Lower is better DVFS Pipe DVFS R2C Auto Global Fig. 6. Objective value and average CPU frequency of dynamic and autonomic systems across various traffic scenarios. Lower values are better. 3.2 Comparison of Autonomic and DVFS Systems Figure 6 compares the globally optimized autonomic system presented in the previous section with two systems that employ dynamic voltage and frequency scaling (DVFS). DVFS allows the non-autonomic system to adjust its operating frequency in a fashion similar to the autonomic frequency actuator. The pipelined dynamic system corresponds to a DVFS-enhanced version of the hand-optimized static system from section 3.1. The dynamic run-to-completion system combines all tasks necessary for the processing of a packet onto a single CPU, allowing each of the system’s three CPUs to completely process any packet type. Looking at the objective function at the top of Figure 6, it can be seen that the autonomic system achieves results quite similar to those of the dynamic run-to-completion system. The difference in objective and frequency values for the first burst is due to the fact that only two CPUs are utilized by the run-to-completion system, since the processing time of the incoming packets is less than twice the interarrival rate. The first CPU has therefore completed processing before the third packet arrives, which means that at least one CPU is idle at any point in time. This results in two CPUs performing all the work, and keeps their workload high enough that the DVFS controller does not further reduce their frequency. Since the minimum frequency of a CPU in these simulations is 50 MHz, even for one that is idle, this results in a
Latency (µs) 30 25 20 15 10 5 0 0 s Autonomic Workload Management for Multi-core Processor Systems 59 4 ms 8 ms 12 ms Fig. 7. Packet latency across various traffic scenarios 16 ms 20 ms 24 ms 28 ms Static Opt. DVFS R2C Auto Global system-wide average frequency which is larger than that of the pipelined and autonomic systems, which split the load across all three CPUs. This also increases the delta value for workload (recall equation 4 from section 2.3.3) of the run-tocompletion system, which further worsens the system’s objective value. Figure 7 shows the impact that the autonomic enhancements have on the packet latency, a global system behavior of which the autonomic evaluator is neither aware, nor has a direct influence over. At the beginning of each burst, the packet latency of the autonomic system shows a brief increase as the system adapts itself to the change in workload. Thereafter, the autonomic enhancements optimize the system such that the packet latency remains nearly constant at 10 µs across all traffic scenarios. During the sixth burst, where the packet latency rises slightly above this value, the autonomic system continues to search for a more preferable system configuration, but is interrupted prior to finding one by the following burst. 4 Conclusion and Future Work In this paper, we have demonstrated the applicability of self-organization concepts and HW-based machine learning techniques for the run-time binding of SW tasks to homogeneous multi-core processors. SW application developers can follow established design flows for functional partitioning of applications into sub-functions (tasks) without being forced to consider the underlying parallel MP-SoC HW architecture. LCT-based hardware evaluators take care of balancing CPU workloads among available processing resources, without requiring a special programming language or fundamental OS modifications. It has been shown that the autonomic system is capable of parameterizing a pipelined architecture so that it performs similarly to a comparable, DVFS-enabled run to completion architecture. The resulting system combines the benefits of both architecture types, while delegating solution of the disadvantages, most notably the difficulty of efficiently distributing the workload of a pipelined system, to the autonomic layer. Further work is planned for the completion of an FPGA hardware prototype to verify the presented simulation results in a functional MP-SoC, and to show that resource overheads are as small as preliminary synthesis results seem to indicate. We also plan to fully investigate the stability of the resulting system, although our simulations so
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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How to Enhance a Superscalar Proces
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4 J. Mische et al. The Real-time Vi
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6 J. Mische et al. 4.1 Instruction
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108 K. Kloch et al. Relative number
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110 K. Kloch et al. (a) infection r
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112 K. Kloch et al. (ii) Phase of a
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122 P. Petoumenos et al. As long as
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124 P. Petoumenos et al. comparable
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Exploiting Inactive Rename Slots fo
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128 M. Kayaalp et al. In a supersca
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130 M. Kayaalp et al. INSTRUCTION 1
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132 M. Kayaalp et al. time. Alterna
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134 M. Kayaalp et al. Fig. 3. Numbe
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136 M. Kayaalp et al. The results o
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Efficient Transaction Nesting in Ha
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140 Y. Liu et al. HTMs include TCC
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142 Y. Liu et al. rollback T0 begin
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144 Y. Liu et al. Processor core Pr
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146 Y. Liu et al. 5.2 Results and A
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148 Y. Liu et al. decreases, partia
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Decentralized Energy-Management to
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152 B. Becker et al. Furthermore, t
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154 B. Becker et al. An optimizing
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156 B. Becker et al. smart-home man
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158 B. Becker et al. freedom like w
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160 B. Becker et al. Power [W] 4500
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EnergySaving Cluster Roll: Power Sa
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172 M.F. Dolz et al. at the inactiv
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Effect of the Degree of Neighborhoo
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176 T. Abdullah et al. A zone based
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178 T. Abdullah et al. A consumer/p
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180 T. Abdullah et al. Messages 140
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184 T. Abdullah et al. % Matchmakin
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226 F. Nowak and R. Buchty Fig. 3.
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228 F. Nowak and R. Buchty Table 2.
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230 F. Nowak and R. Buchty Table 4.
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244 F. Xudong et al. 5 Related Work
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Abdullah, Tariq 174 Alima, Luc Onan
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