Architecture of Computing Systems (Lecture Notes in Computer ...

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52 J. Zeppenfeld and A. Herkersdorf Fig. 2. Autonomic MP-SoC Network Processor Architecture abstractly using fixed access delays to improve simulation performance, and could correspond either to an internal memory or to a memory controller connected to an off-chip RAM. 2.2 Application Software The main focus of this paper is on workload management, which becomes more complex and “interesting” with an increasing number of processing tasks. In order to preserve maximum flexibility and the ability to run the application on a generic MP-SoC platform (shown in Figure 2), as many packet processing functions as possible are implemented as software tasks that can be moved freely among the system’s CPUs. This also includes tasks such as transferring data between the MAC and memory, which alternatively could be accomplished easily – and perhaps more efficiently – by a dedicated hardware DMA controller. In our application, every packet passes through five stages of execution: Task 1: Transfer packet from MAC to memory Task 2: Determine type of processing to be done on present packet Task 3.1 through 3.N: Perform one of N packet header or payload processing tasks Task 4: Reorder packets for in-order transmission Task 5: Transfer packet from memory to MAC While Tasks 1, 2, 4 and 5 are identical for every packet, Task 3 can be different for different packet types. In principle, this task assembly allows for two orthogonal programming models on a generic hardware platform as introduced in Figure 2: Either balance incoming packets across all currently idle CPUs and execute all tasks for a packet on one and the same CPU (Run to Completion (RTC) model), or distribute the tasks among all CPUs and let each packet traverse the CPUs in a pipelined fashion (Pipelined model). Both models have unique characteristics, and both have advantages and disadvantages. RTC treats all cores as independent processing elements, thus eliminating the need for
Autonomic Workload Management for Multi-core Processor Systems 53 complex task partitioning among cores. RTC is easily scalable, but relies on no packet data sharing being required, and that the nature of the application leans towards event / packet balancing. Pipelining requires equal workload sharing of tasks among processing elements in order to achieve optimized throughput and efficiency (avoiding pipeline “bubbles”). On the positive side, the pipelining model is applicable to a larger class of parallel applications, achieves a smaller instruction footprint and supports local state and data caching. 2.3 Autonomic Layer The autonomic layer used for this paper’s simulations contains an autonomic element for each of the system’s three CPUs. Autonomic elements for the bus, memory, MAC and interrupt controller are not included, as the CPUs are currently our primary target for optimization. However, AEs for the remaining functional elements are being considered for future development. Along with an LCT evaluator, the CPU AEs contain several monitors and actuators to interact with the associated CPU FE. Each of these will be discussed in more detail in the following sections. 2.3.1 Monitors Two local monitors keep track of the current CPU frequency and utilization, and are multiplied together to produce a third monitor value – the CPU’s workload: LoadCPU = UtilCPU · FreqCPU (1) Whereas the utilization indicates the percentage of cycles that the CPU is busy (i.e. is processing a packet rather than waiting in an idle loop), the workload indicates the actual amount of work that the CPU is performing per unit of time (useful cycles per second). Since the resulting value is helpful in comparing the amount of processing power being contributed by each CPU, it is shared with the other AEs over the AE interconnect. The workload information can then be averaged over all three CPUs, and by comparison with its own workload allows each CPU to determine whether it is performing more or less than its “fair share” of work. The difference between the CPU’s and the average workload therefore provides another useful monitor value. 2.3.2 Actuators In order to allow the AE to effect changes in CPU operation, two actuators are provided. The first of these simply scales the frequency by a certain value. Note that this is a relative change in frequency, i.e. the new frequency value depends on the old, which makes it easier to provide classifier rules that cover a larger range of monitor inputs. For example, with relative rules it is possible to express the statement “when utilization is high increase the frequency” using a single classifier rule, which would not be possible with an absolute actuator that sets the frequency to a fixed value. The second actuator triggers a task migration from the AE’s CPU to one of the other CPUs. After migration of a task, any further interrupts to start the execution of that task will be serviced by the target CPU instead. If a task migration is triggered while the task is already running, execution of the task is completed first (nonpreemptive task migration). This minimizes the amount of state information that needs to be transferred from one core to another, reducing the performance impact of
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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130 M. Kayaalp et al. INSTRUCTION 1
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148 Y. Liu et al. decreases, partia
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Decentralized Energy-Management to
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Abdullah, Tariq 174 Alima, Luc Onan
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