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Architecture of Computing Systems (Lecture Notes in Computer ...

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34 T.B. Preußer, P. Reichel, and R.G. Spallek<br />

Duration <strong>in</strong> Clock Cycles<br />

Table 1. Device Utilization <strong>of</strong> Reference Platform<br />

Cores FFs LUTs BRAMs<br />

1 3206 7813 10<br />

2 4465 11396 17<br />

3 5720 14963 24<br />

n ≈ 1257n + 1950 ≈ 3575n + 4240 7n +3<br />

120000<br />

100000<br />

80000<br />

60000<br />

40000<br />

20000<br />

0<br />

0 100 200 300 400 500<br />

Liv<strong>in</strong>g Weak Reference Proxies<br />

Heap Scan<br />

Weak Process<strong>in</strong>g<br />

Fig. 6. Overhead <strong>of</strong> Weak Reference Process<strong>in</strong>g<br />

memory access manager as well as through regular Wishbone I/O for less timecritical<br />

operations. The latter also provides fundamental statistical data that we<br />

used for this evaluation. The runtime library was extended to enable application<br />

access to the new features and to provide implementations for the reference<br />

proxy and the reference queue classes. It was also turned <strong>in</strong>to the first client <strong>of</strong><br />

the weak reference support by the implementation <strong>of</strong> resource pools, which, for<br />

<strong>in</strong>stance, enable the proper <strong>in</strong>tern<strong>in</strong>g <strong>of</strong> str<strong>in</strong>gs.<br />

The reference design was implemented on a Xil<strong>in</strong>x Spartan-3 XC3S1000, which<br />

is capable <strong>of</strong> hold<strong>in</strong>g up to three SHAP cores next to the memory management<br />

unit. The utilization <strong>of</strong> this reference platform is summarized <strong>in</strong> Tab. 1. As <strong>in</strong>dicated,<br />

the demand on active resources grows l<strong>in</strong>early with the number <strong>of</strong> <strong>in</strong>tegrated<br />

SHAP cores. While most <strong>of</strong> the basic core-<strong>in</strong>dependent flip-flops and<br />

LUTs may be attributed to the central memory management, global Wishboneattached<br />

IO accounts for about a quarter <strong>of</strong> it. The three Block RAMs outside<br />

the cores are used as MCU storage also conta<strong>in</strong><strong>in</strong>g the GC program and the<br />

global mark table.<br />

The process<strong>in</strong>g <strong>of</strong> liv<strong>in</strong>g weak reference proxies constitutes a process<strong>in</strong>g overhead<br />

as they are enlisted dur<strong>in</strong>g the heap scan to be revisited thereafter <strong>in</strong> order<br />

to verify that their referents have been reached or to clear and enqueue them.<br />

This overhead grows l<strong>in</strong>early with the number <strong>of</strong> liv<strong>in</strong>g proxy objects. This is

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