Architecture of Computing Systems (Lecture Notes in Computer ...

Complexity-Effective Rename Table Design for Rapid Speculation Recovery 19
Fig. 3. Amount of register usage in the Spec2000 benchmark suite, light area represents maximum
usage, dark area represents average usage
Conditions for vacating entries inside the FIFO queues vary according to the implementation
of register renaming inside the processor. In P6 architecture the reorder
buffer entries also serve as physical registers and a separate architectural register file
exists to hold the architectural state. Therefore the head pointer is updated when an
instruction that targets the corresponding architectural register commits. On the other
hand, in architectures, which use a unified register file that holds both the physical
and architectural state, such as the Intel’s Pentium 4 [3], Alpha 21264 [5] and MIPS
R10000 [7], a physical register is released only when an instruction that renames the
same architectural register commits. In the proposed rename structure, the head
pointer of the corresponding architectural register is updated (incremented by one
unless the pointer is at the end of the buffer) whenever a physical register that holds
an instance of the architectural register is released.
Since each architectural register has its own circular FIFO buffer in the proposed
structure, the number of entries in each FIFO queue may vary. The number of entries
for each architectural register can be determined by observing the common behavior
of programs and compilers. If an instruction targets an architectural register and the
corresponding FIFO queue does not contain any available entries, the pipeline stalls
and the frontend waits until an entry is available for the instruction. In order to minimize
the performance degradation due to the proposed rename structure, the FIFO
queues have to be sized appropriately, so that the pipeline does not get stalled frequently.
Fig. 3 shows the average and maximum number of renamed instances of each
general purpose architectural register in the simulated x86 architecture. As the results
reveal, some of the registers are employed more than the others. For example, register
rax has the most concurrent instances on average. This result shows that a larger FIFO
queue has to be used for rax.
The number of entries in each FIFO queue can be at most equal to (the number of
physical registers – the number of architectural registers). This is because of the fact
that each architectural register has to have a physical location and the same physical
register cannot be assigned to two different architectural registers at the same time.