Architecture of Computing Systems (Lecture Notes in Computer ...

A Method for Accurate High-Level Performance Evaluation 201
between dedicated HW accelerators and CPUs is performed. The paper shows
examples of the performance estimation using traces and discusses origins of the
errors produced by the proposed method.
2 Related Work
Performance evaluation of SoC architectures using high level models has been
addressed in many research works. One of possible solutions for obtaining accurate
timing information at system level is the integration of instruction set
simulators into high-level SystemC models. MPARM [2] is a simulation platform
for MPSoC architectures, in which a cycle accurate model of an ARM
processor is integrated into SystemC environment. In [4], an ISS is co-simulated
with SystemC using the GDB-kernel. In this method, the high level model receives
timing information via commands sent through the debugging interfaces.
However, the integration of the instruction set simulators significantly decreases
the simulation performance.
Along with HW/SW co-simulation using an ISS, there is another modeling
principle in which precise timing information is back-annotated to abstracted
high-level simulations. This method is widely used in software code instrumentation
techniques. In [12], a target C code is used to generate a SystemC code
in which the execution time is partially determined at the compilation time. In
turn, dynamic timing information, e.g. effects of caches and branch predictors, is
obtained at simulation runtime using the models of the architecture components.
In [6], a target code is instrumented with additional functional calls for keeping
a count of the executed cycles and for accessing the TLM communication
infrastructure.
In [7], the authors show how traces can be employed for generation of communication
analysis graphs which are later used for evaluation of on-chip communication
architectures. In Sesame [10] and Spade [8] frameworks, traces are used
to represent the workload of multimedia application models constructed using
Kahn Processing Networks (KPN). However, in these approaches the range of
target applications is restricted to those that are adaptable to the KPN model
of computation. Moreover, processing latencies and communication transactions
specified by these traces are very coarse-grained, i.e. delay entries represent large
blocks of computation. At this granularity level, exact memory traffic, which can
significantly influence the application performance, is not addressed. For example,
during the computation of a KPN process, contention of multiple CPUs
on the shared on-chip interconnect during cache misses cannot be considered at
this abstraction level. In our method, traces specify precise patterns of memory
accesses and processing latencies allowing for more accurate analysis of the
application workload.
S. Mahadevan et al. demonstrated a technique in which traces, obtained from
a cycle accurate CPU simulator, are used to represent the component’s behavior
exactly captured at its bus interface [9]. Contrarily, in our method we define the
traces at the instruction level and explicitly model the cache component which