Architecture of Computing Systems (Lecture Notes in Computer ...

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6 J. Mische et al. 4.1 Instruction Fetch The execution of an instruction typically occupies one pipeline stage for only one cycle and issuing multiple instructions from one thread is only reasonable, if there are enough instructions available. Hence the number of instructions that is fetched per cycle must be equal or greater than the number of instructions that can be issued concurrently. As the number of concurrent instructions is equal to the number of pipelines, this number must be multiplied with the maximum instruction length to get the required fetch bandwidth. Assuming a zero cycle memory latency, it takes two cycles from the decision, that a new fetch must be initiated (in the issue stage) until the arrival of the data at the instruction window (again in the issue stage). Therefore the instruction windows (IW) must be large enough to hold at least two times the fetch width. Each additional memory latency further increases the size of the IW by the fetch width. If the instruction width varies and the instructions are not aligned to the borders of the fetch words, the size must be further increased. A concrete example with the CarCore architecture: There are two pipelines and an instruction can be 16 or 32 bits wide. Accordingly, fetching 64 bits should provide at least enough instructions for one cycle. If in cycle t + 0 the RTI issues two instructions to the pipelines it removes at most 64 bit from the IW and recognises that it should be refilled and initiates a fetch. During cycle t +1the memory is accessed and the RTI must take the next 64 bits from the IW. In cycle t + 2 the fetched data arrives at the RTI, so the data can be directly issued to the pipelines. But 128 bits are still not enough, as TriCore instructions must only be aligned to 16 bit boundaries, consequently four instructions could cover three 64 bit words and the minimum IW size is 192 bits. With the proposed fetch width and instruction windows size optimal execution of the highest priority thread (HPT) can be guaranteed. But what about the other threads? The HPT only fully occupies the fetch stage, if there is code that uses every pipeline in every cycle and if these instructions are of maximum length. As the evaluation shows, this is almost never the case. Whenever the IW of a thread is full, the fetch logic tries to fetch for the thread with the next highest priority. Again, the evaluation shows that empty IWs are only a minor reason for not executing a lower priority thread. There are two possibilities to optimise the fetching: The first one called ENOUGH exactly counts how much instructions are in the IW and how they are mapped to pipelines. If there are enough instructions to cover two cycles, further fetches to this thread are delayed, no matter if the IW is already full or not. The AHEAD logic stops fetching when it recognizes a branch somewhere within the IW. This optimisation is only applicable if there is no branch prediction and if there are at least two pipeline stages between fetch and branch decision. An example for the CarCore architecture with three stages between fetch and branch decision (RTI, decode and execute): If in cycle t +0 only the branch is in the IW, the RTI issues it and removes the instruction from the IW. In cycle t +1 the AHEAD logic recognises that there is no longer a branch in the IW and permits to fetch the next instruction. In cycle t + 2 the next instruction
How to Enhance a Superscalar Processor 7 Algorithm 1. Policy of the Real Time Issue Stage Input: number of threads T , number of pipelines P thread0 has the highest priority, threadT −1 the lowest Output: assignment of instructions to pipelines in pipelinep pipelinep ←∅ ∀0 ≤ p
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Abdullah, Tariq 174 Alima, Luc Onan
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