Architecture of Computing Systems (Lecture Notes in Computer ...

Complexity-Effective Rename Table Design for Rapid Speculation Recovery 21
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Fig. 4. The Checkpoint Table used for branch instructions
same cycle with the reading of information from the checkpoint table, for a pipelined
implementation, the processor may read the tail pointers in the first cycle and restore
the rename table in the second cycle.
6 Hardware Implementation
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The rename tables, like any regular memory structure used in contemporary microprocessors,
are implemented by employing SRAM bitcells. While in the architectures
that make use of waiting or walking forward/backward schemes plain SRAM bitcells
are enough for implementation, each bitcell is needed to have a shift register capability
in order to use checkpoints inside the rename table. If there are 16 checkpoints
allowed inside the processor each bit of the rename table needs to be a 16-bit shift
register.
Our proposed rename table scheme removes the shifting complexity at bitcell level
and implements all of the FIFO queues with plain SRAM bitcells. Each FIFO queue is
in fact a small payload RAM that has the same bit-width as a rename table but has a
larger number of entries.
In the baseline 4-way architecture the rename table must have 4 write ports (in case
4 instructions rename different architectural registers) and 8 read ports (in case each
instruction has a different set of architectural source registers). This structure is accessed
after the dependency checking logic detects any possible multiple renames in a
single cycle. Our solution does not alter the dependency checking logic but offers a
different storage mechanism for the register mappings.
In an architecture with N architectural registers, our proposed scheme mandates the
use of N FIFO tables that are made of SRAM bitcells. Each table is a regular payload
RAM with regular decoder circuits that allow random access. However the inputs to
these decoders are wired to the tail pointer register of the corresponding FIFO instead
of taking the values from incoming instructions. The instructions that are renamed
only write their tags though the regular bitlines to the entry (or entries) automatically
selected by the tail pointer register. Note that although, in a 4-way machine, up to 4
values can be written to a FIFO in the same cycle, only one value is read. Therefore
each FIFO structure needs 4 write ports and 1 read port. Also, it should be noted that
although the structure can be accessed randomly like a regular register file, the access
is not random; at each cycle the value that is pointed by the tail pointer is read and if
the corresponding architectural register is renamed up to 4 values are written to the
following entries. The tail pointer is updated after the new register assignments are
written. All of the FIFO queues are circular buffers. Therefore the tail pointer points
to the top of the structure after reaching the bottom.
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