Architecture of Computing Systems (Lecture Notes in Computer ...

20 G. Aşılıoğlu, E.M. Kaya, and O. Ergin
5 Recovering from Branch Mispredictions
The proposed structure allows rapid recovery of the rename table as all of the speculative
register assignments are available in direct mapped SRAM bitcell array. In the
case of a branch misprediction, fixing the tail pointers is enough to recover the rename
table. Different schemes can be employed by using the proposed rename table
structure to rollback the speculation on a branch instruction. For a processor that waits
until the faulting branch reaches the top of the rename table, there is no need to keep a
commit rename table since when the branch reaches the top of the ROB, the head
pointers for each architectural register will point to the precise state. In fact, the head
pointers in the proposed structure form the commit rename table when they are used
together which alleviates the need to store a separate commit rename table as implemented
in some modern microprocessors.
Walk backward and walk forward schemes get easier to implement with the
proposed design since nothing in the rename table is overwritten during the rename
process. During the walk backward operation, the processor just decrements the corresponding
tail pointer of the architectural register that is targeted by the squashed
instruction. When the faulting branch instruction is reached, the tail pointers of all
FIFO queues are restored.
Checkpointing becomes simpler at the circuit level by using the proposed rename
table design. Regular checkpointing requires a shadow copy taken at each branch
instruction. This is accomplished by implementing each bit of the rename table as a
shift register. Since the number of checkpoints limits the number of branch instructions
that can reside inside the processor concurrently, having more checkpoints is
desirable. However, as the number of checkpoints increases, the logic depth for an
individual shift register increases, which results in a higher rename table latency and
limits the frequency of the processor. The use of the proposed scheme allows implementing
the checkpointing scheme more easily without any need for shift registers.
Instead of checkpointing the entire table on each branch, the tail pointers for each
architectural register are stored in a table whenever a branch instruction arrives at the
rename stage. This table is indexed by the branch identifiers and has to be implemented
as a circular FIFO queue since nested branch instructions may require squashing
multiple branch instructions in program order.
Fig. 4 shows the structure of the checkpoint table used to store the information for
each branch instruction. For each entry, a tail pointer is stored for each architectural
register. Since the size of each FIFO queue can be at most equal to the number of
physical registers, each stored tail pointer can be represented with log2(number of
physical registers). For a processor with 256 registers, tail pointers are 8-bits long,
resulting in 64 bits for each entry in the checkpoint table. Therefore the latency of this
structure is similar to the register file itself depending on the number of branches
allowed inside the processor. Whenever the outcome of a branch is mispredicted, the
processor accesses the checkpoint table with branch index and reads the stored tail
pointers. The tail pointer registers of the rename table are overwritten by the tail
pointer values read from the checkpoint table in order to recover the rename table to
the cycle just before the faulting branch instruction. Depending on the circuit level
implementation and the clock frequency of the processor, restoring the rename table
may take one or two cycles. While it can be possible to fix the tail pointers in the