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Architecture of Computing Systems (Lecture Notes in Computer ...

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Activate Write Barrier<br />

Local Root Scans<br />

Central Heap Scan<br />

Deactivate Write Barrier<br />

Process Weak References<br />

Recycle Reference Handles<br />

An Embedded GC Module with Support for Multiple Mutators 29<br />

Fig. 2. GC Cycle Overview<br />

Evacuate<br />

Sparse<br />

Segments<br />

Full<br />

Compaction<br />

Alive Objects<br />

Empty Used<br />

FIFO FIFO<br />

Allocation Eng<strong>in</strong>e<br />

Sparse<br />

Fig. 3. Segment Life Cycle<br />

provides the strong advantages <strong>of</strong> a concise design structure, lower resource demand<br />

and a high achieved clock frequency. In fact, an OpenFIRE solution would<br />

require a second slower clock doma<strong>in</strong> or the reduction <strong>of</strong> the overall system clock<br />

by 40%. Consequently, it was the ZPU microarchitecture, which we chose to be at<br />

the heart <strong>of</strong> our memory management.<br />

As illustrated <strong>in</strong> Fig. 1, the ZPU assumes the central control <strong>of</strong> the memory<br />

management as memory control unit (MCU). It is surrounded by several<br />

special-purpose hardware components implement<strong>in</strong>g time-critical subtasks. The<br />

connection to the system Wishbone bus enables the slow adm<strong>in</strong>istrative communication<br />

with the mutator cores. This not only serves the communication <strong>of</strong><br />

statistics data but is also used for deliver<strong>in</strong>g weak reference proxies to the runtime<br />

system for their possible enqueu<strong>in</strong>g <strong>in</strong>to reference queues so that our design<br />

supports this feature <strong>in</strong> addition to the CLDC requirements.<br />

The memory access <strong>of</strong> the mutator cores are prioritized over GC-related accesses.<br />

The garbage collector, thus, operates on cycle steal<strong>in</strong>g, a very f<strong>in</strong>e-gra<strong>in</strong>ed<br />

utilization <strong>of</strong> otherwise idle memory bandwidth.<br />

The overall GC cycle is summarized <strong>in</strong> Fig. 2. It is <strong>in</strong>itiated and supervised<br />

by the MCU. Individual tasks are, however, backed by dedicated hardware components<br />

conta<strong>in</strong><strong>in</strong>g small specialized state mach<strong>in</strong>es.<br />

3.2 GC Strategy<br />

The organization <strong>of</strong> the heap memory must enable both the prompt allocation<br />

<strong>of</strong> objects as well as a steady recycl<strong>in</strong>g <strong>of</strong> unused memory. We chose a simple<br />

yet efficient bump-po<strong>in</strong>ter allocation scheme. While it guarantees an <strong>in</strong>stant<br />

allocation, it also requires the compaction <strong>of</strong> the used memory as to re-generate<br />

the cont<strong>in</strong>uous allocation region.

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