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60 J. Zeppenfeld and A. Herkersdorf<br />

far have shown that with a reasonable <strong>in</strong>itial rule set, optimization generally occurs<br />

only for a short period follow<strong>in</strong>g a change <strong>in</strong> workload, after which the system behavior<br />

enters a stable state. F<strong>in</strong>ally, <strong>in</strong> addition to the autonomic elements connected to<br />

the CPU cores, further AEs are planned for the bus, memory and I/O modules. This<br />

will enable the parameterization <strong>of</strong> all system components, and provide additional<br />

global monitor signals to allow an even better optimization <strong>of</strong> the autonomic system.<br />

Acknowledgements<br />

We would like to thank our project partners Abdelmajid Bouajila and Walter Stechele<br />

from the Technische Universität München, Andreas Bernauer and Wolfgang Rosenstiel<br />

from the University <strong>of</strong> Tüb<strong>in</strong>gen, and Oliver Br<strong>in</strong>gmann from the FZI <strong>in</strong><br />

Karlsruhe. The ASoC project is sponsored by the DFG under SPP 1183 Organic<br />

<strong>Comput<strong>in</strong>g</strong>.<br />

References<br />

[1] S<strong>in</strong>ghal, R.: Inside Intel Next Generation Nehalem Microarchitecture,<br />

http://blogs.<strong>in</strong>tel.com/idf/2008/08/<br />

sample_idf_sessions_<strong>in</strong>side_neh.php<br />

[2] Held, J., Bautista, J., Koehl, S.: From a Few Cores to Many: A Tera-scale <strong>Comput<strong>in</strong>g</strong> Research<br />

Overview. White Paper, http://www.<strong>in</strong>tel.com<br />

[3] Henkel, J.: Clos<strong>in</strong>g the SoC design gap. <strong>Computer</strong> 36(9), 119–121 (2003)<br />

[4] Wang, Z.: Mapp<strong>in</strong>g Parallelism to Multi-cores: A Mach<strong>in</strong>e Learn<strong>in</strong>g Based Approach. In:<br />

14th ACM SIGPLAN Symposium on Pr<strong>in</strong>ciples and Practice <strong>of</strong> Parallel Programm<strong>in</strong>g, pp.<br />

75–84 (2009)<br />

[5] Streichert, T., Strengert, C., Haubelt, C., Teich, J.: Dynamic Task B<strong>in</strong>d<strong>in</strong>g for Hardware/S<strong>of</strong>tware<br />

Reconfigurable Networks. In: SBCCI 2006, pp. 38–43 (2006)<br />

[6] Li, J., Ma, X., S<strong>in</strong>gh, K., Schulz, M., de Sup<strong>in</strong>ski, B., McKee, S.: Mach<strong>in</strong>e Learn<strong>in</strong>g Based<br />

Onl<strong>in</strong>e Performance Prediction for Runtime Parallelization and Task Schedul<strong>in</strong>g. In:<br />

ISPASS, pp. 89–100 (2009)<br />

[7] Bernauer, A., et al.: An <strong>Architecture</strong> for Runtime Evaluation <strong>of</strong> SoC Reliability. In: Informatik<br />

für Menschen. <strong>Lecture</strong> <strong>Notes</strong> <strong>in</strong> Informatics, vol. P-93, pp. 177–185 (2006)<br />

[8] Zeppenfeld, J., Bouajila, A., Stechele, W., Herkersdorf, A.: Learn<strong>in</strong>g Classifier Tables for<br />

Autonomic <strong>Systems</strong> on Chip. <strong>Lecture</strong> <strong>Notes</strong> <strong>in</strong> Informatics, vol. 134, pp. 771–778.<br />

Spr<strong>in</strong>ger, Gesellschaft für Informatik (2008)<br />

[9] Wilson, S.: Classifier fitness based on accuracy. Evolutionary Computation 3, 149–175<br />

(1995)

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