Architecture of Computing Systems (Lecture Notes in Computer ...

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238 F. Xudong et al. stencil computations of Mgrid, many intermediate results can be reused. Reusing these results reduces memory fetches as well as computation. Generally, large thread granularity can improve data locality and computation intensity, though entailing the consumption of more GPRs. We will explain the concept of thread granularity later. Given limited resources (such as the number of GPRs, memory bandwidth) and the amount of work (e.g., a specific kernel computation), the number of threads that can be created is determined bythreadgranularity.Inotherwords, the thread granularity is in inverse proportion to the number of threads. This means tuning thread granularity can balance locality within thread and parallelism among threads [8]. So there should be a balance between thread locality and thread parallelism through tuning. To achieve the best performance, programmers should carefully tune the thread granularity to strike the right balance. In Brook+, the total number of threads is determined by the output stream size (domain size). Note that the thread granularity here means the number of grid points a thread calculates. There are two methods to tuning thread granularity in Brook+: (a) Using vector types Brook+ provides built-in short vector types for tuning the code explicitly on the available short-SIMD machines. Short vectors here are built from the name of their base type, with the size appended as a suffix, such as float4 and double2. Using vector types reduces the domain size (the output stream length) by a factor of the vector size, and consequently increases the thread granularity by the same factor. Take double2 for example. Using double2 increases the thread granularity by a factor of two. A thread can now compute two stencil points at a time, so more data reuse can be exploited through using the intermediate results within each thread. Moreover, using vector types can pack up to four scalar fetches into one vector fetch to form a vector fetch. Vector fetch significantly reduces memory fetches if a kernel is designed to fetch from consecutive data locations, thus making more efficient use of the fetch resources. For example, a kernel can issue a float4 fetch in one cycle versus four separate float fetches in four cycles. In the stencil computations of Resid where locations of the data to be fetched are usually consecutive, vector fetches naturally raise arithmetic intensity and improve memory performance. (b) Multiple output streams Brook+ supports up to eight simultaneous output streams per kernel using the CAL backend [1]. Using multiple output streams, a thread can complete multifolds of computations with respect to using a single output stream, which also increases the thread granularity. For example, using two output streams doubles the thread granularity. If we combine vector types and multiple output streams together, even larger thread granularity can be attained. For instance, using double2 and four output streams together, we increase the thread granularity by a factor of eight (24=8).
Optimizing Stencil Application on Multi-thread GPU Architecture 239 However, using vector types needs modification of indices in the kernel body, and adopting multiple output streams requires splitting the input streams. Also, both methods increase the requirement for GPRs and consequently reduce the number of active threads that can be created. Whether these kinds of overheads incurred can be offset by the performance gain of tuning thread granularity is determined by kernel size and specific kernel characteristics. As for what thread granularity is best, we should determine this through experiments. 3.2 Stream Reorganization Although memory access with texture unit (memory) supports 1D, 2D and 3D addressing modes, the texture cache is optimized for 2D locality. In order to exploit more data locality in the cache, the threads in the same wavefront should read texture addresses that are close along two dimensions. This process may need transformation on data layout or data structure. Taking the implementation of the Resid kernel on the GPU for example, the runtime library would automatically linearly expand 3D data streams into 2D data streams. This transformation may impact the cache performance, because the computation needs to access adjacent data in three dimensions. To get better performance, the 3D stream should be transformed into a 2D stream in the block manner. The process is illustrated in Fig. 1(a). Compared with the layout in the linearly expanding manner, the data adjacent in the logical space is kept adjacent in the 2D stream. The Resid kernel refers data on three consecutive planes when performing stencil computations for a grid point. After stream reorganization, we exploit the cache data locality within each plane. 4 2 1 3 1 2 3 4 (a) resid Level N norm3 GPU CPU Level N-1 rprj3 rprj3 Level 2 rprj3 Level 1 resid psinv interp (b) Level 1 interp Level 2 interp Level N Level N-1 resid psinv resid psinv norm3 Finest Grid resid psinv Coarsest Grid Fig. 1. (a) Transforming the 3D stream into 2D stream in the block manner [9] (b) V-cycle pattern of Mgrid 3.3 Branch Elimination GPUs adopt SIMD execution mode, which incurs large flow control overhead. Take branching for example. AMD GPUs combine all the necessary paths as a wavefront. However, even if only one thread within a wavefront diverges, the rest of the
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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How to Enhance a Superscalar Proces
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4 J. Mische et al. The Real-time Vi
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8 J. Mische et al. Additionally the
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10 J. Mische et al. % of unused pip
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26 T.B. Preußer, P. Reichel, and R
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102 K. Kloch et al. large-scale sys
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106 K. Kloch et al. constant. This
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Exploiting Inactive Rename Slots fo
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128 M. Kayaalp et al. In a supersca
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130 M. Kayaalp et al. INSTRUCTION 1
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Efficient Transaction Nesting in Ha
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140 Y. Liu et al. HTMs include TCC
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142 Y. Liu et al. rollback T0 begin
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148 Y. Liu et al. decreases, partia
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