Architecture of Computing Systems (Lecture Notes in Computer ...

Recommendations

Info

134 M. Kayaalp et al. Fig. 3. Number of concurrently renamed instructions different instruction set. These results show that the pipeline stages are full most of the cycles as opposed to our previous findings obtained by using M-Sim [16] for Alpha 21264 instruction set [3]. Fig. 4 shows how much the rename stage is employed in two consecutive cycles. Each horizontal set of bars represents a different benchmark and for each benchmark the statistics show the frequency of consecutive employment situation for the rename stage. For example, the value 44 on the x axis shows how frequent 4 instructions are renamed for two consecutive cycles. The results show that the processor usually switches between empty stage and full stage but does not usually switch from half-full to half-full. The frequency of 12 and 23 situations show this behavior. Also as it can be seen from the figure, 40, 30, 20 and 10 situations are quite common (more than 10% on average). Therefore it makes sense to copy a single tag to a following bubble slots at a full pipeline stage for soft error detection coverage. Fig. 4. Frequency of employment at the rename stage for two consecutive cycles
Exploiting Inactive Rename Slots for Detecting Soft Errors 135 Fig. 5. Reduction of soft error vulnerability in the register tags Fig. 5 shows the vulnerability reduction achieved in the register tags of the instructions by applying the proposed techniques. The bottom part of each bar shows the vulnerability reduction achieved by replicating the source and destination tags of 1 instruction or 2 instructions that are renamed in the same cycle. The middle part of the bar shows the vulnerability reduction achieved by employing the empty stages that come right after an employed rename stage cycle. In this case one of the tags is copied to the slots in the previous stage just after the fetching of the bubble into the pipeline. Finally the top part of the chart is the result when a tag is replicated for soft error detection to an empty slot that comes two cycles after a full stage. As the results reveal there are diminishing returns when we try to exploit farther empty slots while the hardware complexity to check for an error is increased. 6 Conclusion and Future Work In superscalar processors multiple instructions are fetched, decoded, renamed and dispatched each and every cycle. In order to solve the intra group data dependencies, comparator circuits are employed in the rename stage of the pipeline which check if the destination of an older instruction is equal to the sources of a younger instruction. Frequently, because of control dependencies, full fetch width of the machine is not used and the comparators in the rename logic are kept idle until another set of instructions arrive. In this paper we proposed a scheme to detect and correct soft errors by replicating the instruction tags in the frontend of the processor and later checking the equality of these replicated tags at the rename stage of the pipeline by employing the unused comparator circuits. We also show that frequently no instructions are fetched from the memory and the unemployed processor resources during those cycles can be used for error detection for the previously fetched instructions. Our results show that, on the average across all spec benchmarks, more than 20% of the register tags can be protected against any soft errors in the frontend of the processors by employing the proposed techniques.
Page 2 and 3:
Lecture Notes in Computer Science 5
Page 4 and 5:
Volume Editors Christian Müller-Sc
Page 6 and 7:
General Chair Organization Christia
Page 8 and 9:
Organization IX Hartmut Schmeck Kar
Page 10 and 11:
Keynote Table of Contents HyVM - Hy
Page 12 and 13:
Table of Contents XIII JetBench:AnO
Page 14 and 15:
How to Enhance a Superscalar Proces
Page 16 and 17:
4 J. Mische et al. The Real-time Vi
Page 18 and 19:
6 J. Mische et al. 4.1 Instruction
Page 20 and 21:
8 J. Mische et al. Additionally the
Page 22 and 23:
10 J. Mische et al. % of unused pip
Page 24 and 25:
12 J. Mische et al. % of cycles spe
Page 26 and 27:
14 J. Mische et al. 16. Lickly, B.,
Page 28 and 29:
16 G. Aşılıoğlu, E.M. Kaya, and
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
26 T.B. Preußer, P. Reichel, and R
Page 40 and 41:
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
38 P. Bellasi, W. Fornaciari, and D
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 62 and 63:
50 J. Zeppenfeld and A. Herkersdorf
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
62 B. Jakimovski, B. Meyer, and E.
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
74 M. Bonn and H. Schmeck Fig. 1. J
Page 88 and 89:
76 M. Bonn and H. Schmeck 2.2 Node
Page 90 and 91:
78 M. Bonn and H. Schmeck Uptime-ba
Page 92 and 93:
80 M. Bonn and H. Schmeck 2.4 Simul
Page 94 and 95:
82 M. Bonn and H. Schmeck done rate
Page 96 and 97: 84 M. Bonn and H. Schmeck Fig. 8. J
Page 98 and 99: 86 M. Bonn and H. Schmeck tells the
Page 100 and 101: 88 J.-P. Steghöfer et al. � �
Page 102 and 103: 90 J.-P. Steghöfer et al. mechanis
Page 104 and 105: 92 J.-P. Steghöfer et al. resource
Page 106 and 107: 94 J.-P. Steghöfer et al. Choose a
Page 108 and 109: 96 J.-P. Steghöfer et al. 1. Defin
Page 110 and 111: 98 J.-P. Steghöfer et al. and all
Page 112 and 113: 100 J.-P. Steghöfer et al. 19. Kim
Page 114 and 115: 102 K. Kloch et al. large-scale sys
Page 116 and 117: 104 K. Kloch et al. a�t� 1.0 0.
Page 118 and 119: 106 K. Kloch et al. constant. This
Page 120 and 121: 108 K. Kloch et al. Relative number
Page 122 and 123: 110 K. Kloch et al. (a) infection r
Page 124 and 125: 112 K. Kloch et al. (ii) Phase of a
Page 126 and 127: 114 P. Petoumenos et al. Studying t
Page 128 and 129: 116 P. Petoumenos et al. % of Misse
Page 130 and 131: 118 P. Petoumenos et al. IQ: n 4-in
Page 132 and 133: 120 P. Petoumenos et al. downsizing
Page 134 and 135: 122 P. Petoumenos et al. As long as
Page 136 and 137: 124 P. Petoumenos et al. comparable
Page 138 and 139: Exploiting Inactive Rename Slots fo
Page 140 and 141: 128 M. Kayaalp et al. In a supersca
Page 142 and 143: 130 M. Kayaalp et al. INSTRUCTION 1
Page 144 and 145: 132 M. Kayaalp et al. time. Alterna
Page 148 and 149: 136 M. Kayaalp et al. The results o
Page 150 and 151: Efficient Transaction Nesting in Ha
Page 152 and 153: 140 Y. Liu et al. HTMs include TCC
Page 154 and 155: 142 Y. Liu et al. rollback T0 begin
Page 156 and 157: 144 Y. Liu et al. Processor core Pr
Page 158 and 159: 146 Y. Liu et al. 5.2 Results and A
Page 160 and 161: 148 Y. Liu et al. decreases, partia
Page 162 and 163: Decentralized Energy-Management to
Page 164 and 165: 152 B. Becker et al. Furthermore, t
Page 166 and 167: 154 B. Becker et al. An optimizing
Page 168 and 169: 156 B. Becker et al. smart-home man
Page 170 and 171: 158 B. Becker et al. freedom like w
Page 172 and 173: 160 B. Becker et al. Power [W] 4500
Page 174 and 175: EnergySaving Cluster Roll: Power Sa
Page 176 and 177: 164 M.F. Dolz et al. Themodulequeri
Page 178 and 179: 166 M.F. Dolz et al. This daemon al
Page 180 and 181: 168 M.F. Dolz et al. been submitted
Page 182 and 183: 170 M.F. Dolz et al. On the other h
Page 184 and 185: 172 M.F. Dolz et al. at the inactiv
Page 186 and 187: Effect of the Degree of Neighborhoo
Page 188 and 189: 176 T. Abdullah et al. A zone based
Page 190 and 191: 178 T. Abdullah et al. A consumer/p
Page 192 and 193: 180 T. Abdullah et al. Messages 140
Page 194 and 195: 182 T. Abdullah et al. (except when
Page 196 and 197:
184 T. Abdullah et al. % Matchmakin
Page 198 and 199:
186 T. Abdullah et al. show that th
Page 200 and 201:
188 M. Schindewolf, D. Kramer, and
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
200 R. Plyaskin and A. Herkersdorf
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
212 M.Y. Qadri, D. Matichard, and K
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
A Tightly Coupled Accelerator Infra
Page 236 and 237:
224 F. Nowak and R. Buchty where A
Page 238 and 239:
226 F. Nowak and R. Buchty Fig. 3.
Page 240 and 241:
228 F. Nowak and R. Buchty Table 2.
Page 242 and 243:
230 F. Nowak and R. Buchty Table 4.
Page 244 and 245:
232 F. Nowak and R. Buchty 5.3 Comp
Page 246 and 247:
Optimizing Stencil Application on M
Page 248 and 249:
236 F. Xudong et al. compared to th
Page 250 and 251:
238 F. Xudong et al. stencil comput
Page 252 and 253:
240 F. Xudong et al. threads in the
Page 254 and 255:
242 F. Xudong et al. Speedup 14 12
Page 256 and 257:
244 F. Xudong et al. 5 Related Work
Page 258:
Abdullah, Tariq 174 Alima, Luc Onan
show all

Architecture of Computing Systems (Lecture Notes in Computer ...

Create successful ePaper yourself

Delete template?

Save as template?