Architecture of Computing Systems (Lecture Notes in Computer ...

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242 F. Xudong et al. Speedup 14 12 10 8 6 4 2 0 N 2N 4N 8N 32 64 Problem Size N 128 256 3 (a) Speedup 14 12 10 8 6 4 2 0 Resid Psinv Interp Rprj3 Mgrid 9.28x N 2N 4N 8N Thread Granularity Fig. 2. (a) Performance of the kernel Resid under different problem sizes using different thread granularities (b) Speedup of each kernel and Mgrid under the largest problem size 256 3 Fig. 2(b). However, the speedup descends when the thread granularity reaches 8N. This is mainly due to large thread granularity impacting the number of threads being created, even though Interp is an ALU-intensive kernel. Rprj3 computes the finer grid through accessing the coarse grid. There is little data reuse between two grid points, so it is more like a memory intensive kernel. For memory intensive kernels, the way to speedup the execution is to schedule enough threads to hide memory fetch latencies. Therefore, the kernel performance degrades with increasing thread granularity, even though larger thread granularity contributes to more data reuse within each thread to some extend, as we can see the speedup trend of the Rprj3 kernel in Fig. 2(b). The overall speedup of Mgrid peaks in the thread granularity 4N, as shown in Fig. 2(b), which means that when using this thread granularity, we strike the right balance between thread locality and thread parallelism. The largest speedup attained through tuning the thread granularity was 9.28x under the largest problem size. 4.2 Effects of Stream Reorganization Applying the stream reorganization strategy described in Subsection 3.2, we now examine its effectiveness using the Resid kernel. As shown in Fig. 3(a), the speedups increase with the thread granularity under all the problem sizes except the problem size 32 3 . Under all the problem sizes, the speedups in the 2D stream organization are higher than that in the 3D stream organization. This demonstrates that the stream reorganization strategy is very effective. Note that in large thread granularity, the speedups differs sharply between the two data layouts. This is because the 2D version has better cache locality and reduced memory fetch ratio. Therefore more active threads can be created while maintaining the performance gain through increasing the thread granularity. Moreover, when (b)
Speedup 25 20 15 10 5 0 Optimizing Stencil Application on Multi-thread GPU Architecture 243 3D-N 2D-N 3D-2N 2D-2N 3D-4N 2D-4N 32 64 128 256 Problem Size N 3 (a) Speedup 16 14 12 10 8 6 4 2 0 1 6.33 Mgrid Implementation 15.06 CPU GPU- naive GPU-final Fig. 3. (a) Speedup of the Resid kernel in 2D data organization compared to 3D data organization (b) Overall performance improvement the problem size becomes larger, the cache pressure also gets larger. Then the advantage of 2D data layout to 3D data layout will become more evident since the 2D stream organization enhances cache locality. 4.3 Effects of Branch Elimination The Interp kernel computes the interpolation from coarse grid to fine grid. Eight grid points forming a cube in the coarse grid correspond to one grid point in the fine grid, and every point is calculated according to the parity of its x, y and z coordinates. So there are eight conditional branches in the kernel. Using the branch elimination strategy proposed in Subsection 3.3, we eliminate all its eight branches. Our experiment results show that the improved version obtains a speedup of 5.95x over the CPU version and approximately 2.0x speedup over the naive GPU version. This demonstrates that the branch elimination strategy is very effective. 4.4 Effects of CPU-GPU Work Distribution When using the work distribution strategy, we should take a holistic view of the entire system, and reasonably distribute work among the CPU and GPU. In our experiment, we found that the problem size 32 3 is the right partition point, and we assigned the work under the problem size 32 3 back to the CPU. As illustrated in Fig. 1(b), the computations of large problem sizes (larger than 32 3 )above the dotted line are assigned to the GPU, while the others of small problem size below the dotted line are assigned back to the CPU. Finally, we applied all the four optimization strategies to the naive GPU implementation. As shown in Fig. 3(b), the final implementation gained a speedup of 15.06x over the CPU version and 2.38x over the naive GPU version. (b)
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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How to Enhance a Superscalar Proces
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4 J. Mische et al. The Real-time Vi
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Exploiting Inactive Rename Slots fo
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128 M. Kayaalp et al. In a supersca
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130 M. Kayaalp et al. INSTRUCTION 1
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140 Y. Liu et al. HTMs include TCC
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142 Y. Liu et al. rollback T0 begin
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148 Y. Liu et al. decreases, partia
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