Architecture of Computing Systems (Lecture Notes in Computer ...

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202 R. Plyaskin and A. Herkersdorf can be reconfigured during design space explorations. Consideration of the cache effects in high-level models is necessary since caching significantly alters the application performance. In our method, communication latencies are defined at simulation runtime depending on the miss rate of the cache model as well as utilization of the shared on-chip communication infrastructure by other CPU components. Moreover, we focus on the correspondence between the instructions of particular subroutines and their trace representation. This allows the designer to profile the traces during high-level design space explorations. 3 System-Level Simulations Using Traces The workflow for generation of traces and their use in a trace-driven MPSoC simulator is presented in Fig. 2. In the first step, the object code of a crosscompiled application is executed on a cycle accurate simulator of the target CPU. In addition, we deploy an objdump utility to create a symbol table of the code. Information produced by the simulation as well as the symbol table are further processed by a trace generator tool which produces a trace file of the target application. The resulting trace is used as a part of the workload in our trace-driven multiprocessor SystemC TLM simulator, in which diverse (MP)SoC architectures with a varying number of CPUs, different cache models, hierarchical on-chip interconnect can be modeled and analyzed. The simulator is highly configurable by means of an XML description file in which the parameters of the components as well as their interconnection can be specified. In the trace simulator, the resulting traces are executed on the abstract CPU models in a new multiprocessor environment. Thus, the designer can evaluate Fig. 2. Workflow for high-level simulations using traces
A Method for Accurate High-Level Performance Evaluation 203 the impact of shared resources on performance of the application. In addition, the simulator can profile the application traces allowing the designer to identify possible options for HW/SW functional repartitioning. The repartitioning can be performed by a simple trace modification and analyzed in the simulator in an iterative manner. The following sections provide further details on each step of the proposed workflow. 3.1 Generation of Traces In order to estimate the execution time of the target software, cycle accurate CPU simulators typically contain models of micro-architectural components, e.g., branch predictors or instruction pipelines. Using a CPU simulator, the designer can observe the contents of CPU’s internal registers and memory addresses in load and store instructions. For the generation of traces, the order of the instructions as well as their timing information is of the most importance. In a cycle accurate simulation, the executed instructions can be categorized into two types: – Processing instructions not resulting in a request on the bus; – Communication instructions that perform load and store operations. Since none of the processing instructions initiates memory accesses, a group of subsequent processing instructions are translated to a DELAY trace primitive (Fig. 3). The trace generator calculates the overall execution time of this group and stores it as a parameter of the primitive. Correspondingly, the communication instructions are translated to READ and WRITE trace primitives. Information on the destination target of each transaction and the target memory address is stored as primitive’s parameters as well. In order to enable profiling of the application trace, trace primitives are divided into groups. Each group represents an execution of the instructions within a particular subroutine of the target SW code. For each group, the trace generator identifies the subroutines’ names using the symbol table of the target code Fig. 3. Generation of traces using a log file from a CPU cycle accurate simulation
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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130 M. Kayaalp et al. INSTRUCTION 1
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