Architecture of Computing Systems (Lecture Notes in Computer ...

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14 J. Mische et al. 16. Lickly, B., Liu, I., Kim, S., Patel, H.D., Edwards, S.A., Lee, E.A.: Predictable programming on a precision timed architecture. In: CASES 2008, pp. 137–146 (2008) 17. Infineon Technologies AG: TriCore 1 User’s Manual. V1.3.8 (January 2008) 18. HighTec EDV-Systeme GmbH: Website, http://www.hightec-rt.com/ 19. Hennessy, J.L., Patterson, D.A.: Computer architecture: a quantitative approach, 4th edn. Morgan Kaufmann Publishers Inc., San Francisco (2007) 20. Embedded Microprocessor Benchmark Consortiu: AutoBench 1.1 software benchmark data book, http://www.eembc.com/techlit/datasheets/autobench_db.pdf 21. Märdalen WCET research group: Worst Case Execution Time Bechmarks, http://www.mrtc.mdh.se/projects/wcet/benchmarks.html
Complexity-Effective Rename Table Design for Rapid Speculation Recovery Görkem Aşılıoğlu, Emine Merve Kaya, and Oğuz Ergin TOBB University of Economics and Technology Söğütözü Cad. No: 43 Söğütözü Ankara/TÜRKİYE gasilioglu@etu.edu.tr, emkaya@cis.jhu.edu, oergin@etu.edu.tr Abstract. Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that holds the physical register identifiers assigned to each architectural register. This mapping table needs to be recovered to its correct state when a branch prediction occurs. In this paper we propose a scalable rename table design that allows fast recovery on branch predictions. A FIFO scheme is applied with a distributed rename table structure that holds a variable number of checkpoints specific to each architectural register. Our results show that although the area of the rename table is increased, it is possible to recover from a branch misprediction in at worst 2 cycles. Keywords: Register renaming, branch prediction, rename table, speculation recovery. 1 Introduction Superscalar microprocessors use aggressive techniques like out-of-order execution and dynamic scheduling in order to boost performance. Data and control dependencies between the instructions are the major limiting factor on performance during the processor design process. Some data dependencies are in fact not real but result from the lack of architectural registers at compile time and hence are called the “false data dependencies”. In order to remove these false data dependencies and reduce the number of stalls in the pipeline, many of the contemporary microprocessors employ the technique called “register renaming”. In register renaming, a new physical register is assigned for each instruction that produces a result. A register alias table (RAT) is used in the rename stage of the pipeline to keep track of the assignments between the architectural registers and the physical registers. Usually this table (also called the “rename table”) is implemented by using an entry for each architectural register. The rename table holds the precise state of the processor and has to be recovered in the case of an unexpected event, such as a branch mispredicton or exception. Since the time required for restoring the contents of the table add to the branch misprediction penalty, it is crucial that the table is recovered as soon as possible. Different schemes exist in the literature to rollback the branch speculation, of which the most used techniques include checkpointing the C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 15–24, 2010. © Springer-Verlag Berlin Heidelberg 2010
Page 2 and 3: Lecture Notes in Computer Science 5
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Exploiting Inactive Rename Slots fo
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Abdullah, Tariq 174 Alima, Luc Onan
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