Architecture of Computing Systems (Lecture Notes in Computer ...

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4 J. Mische et al. The Real-time Virtual Multiprocessor (RVMP) [15] issues multiple instructions from multiple threads to multiple pipelines, but it assumes multiple identical pipelines and statically maps threads to pipelines. Therefore multiple hard real-time threads can be executed, but the throughput is not increased, as idle pipeline slots cannot be used dynamically by other threads. The Precision Timed (PRET) Architecture [16] is another example of a hard real-time capable multithreaded processor, but again the schedule is very static: there are 6 threads and they are executed in fixed order, hence every thread gets exactly one sixth of the execution time. If a thread is stalled, the cycle cannot be used by another thread, as the PRET architecture supports only precisely timed hard real-time threads, no other threads with softer timing demands can be executed to increase throughput. 3 Baseline Exemplary we use a TriCore compatible processor to present the SMT enhancements, but they can easily be transferred to other superscalar in-order architectures. TriCore-specific parts are explicitly marked. 3.1 TriCore Architecture The Infineon TriCore [17] is a microcontroller that is commonly used in safety-critical applications of the automotive industry. It combines a real-time capable load-store microcontroller architecture with DSP instructions. The instruction set comprises more than 700 instructions. Besides the common arithmetic, logic, branch and load-store instructions it provides instructions for sophisticated logic, context saving, load-modify-store, packed arithmetic, saturated math and multiply-accumulate. The processor consists of a three-way superscalar in-order pipeline with four stages. If an address, an integer, and a loop instruction appear in this order in the instruction stream, they are issued within one cycle, even if they are data-dependent. 3.2 Simplifications for Single-Threaded CarCore As baseline for the SMT enhancement we implemented a cycle-accurate System- C model and a synthesisable VHDL model of a Tricore-compatible processor. It differs from the original Infineon TriCore in the following aspects: Instruction Subset. Special DSP instructions and addressing modes which are never generated by the Hightec [18] compiler are not supported. This reduces the number of instructions to 433, but there is no impact on the execution time, as only pure C code without assembler code snippets is used. Later Address Calculation. CarCore calculates branch target and memory access addresses in the execute stage, one stage later than TriCore. Hence the branch and memory delay slots are increased by one, but the critical path of the very complex and slow decode stage is shortened resulting in a higher overall clock rate.
�� How to Enhance a Superscalar Processor 5 �� Fig. 1. Block diagram of the CarCore architecture �� No Branch Prediction. The HPT does not benefit of a branch prediction, because it only decreases the average, not the worst case execution time. For lower priority threads the benefit is likewise low, as between the branch instruction and the first target instruction usually HPT instructions must be executed anyway. Omitting the speculative execution replaces wasted mispredicted instructions by instructions of lower priority threads that increase the overall throughput. No Loop Pipeline. The TriCore loop pipeline that speeds up special loops is not implemented, as the compiler can use it only in a few special cases and with multithreading the latencies can be used to execute concurrent threads. No Dedicated Context Save Memory. According to the TriCore instruction set architecture, at a subroutine call, 16 registers have to be saved. To speed this up, the Tricore has a special memory area with a very wide bus for context saving. In our version we use the standard memory bus, therefore a function call is about ten times slower. 4 SMT Enhancements To enable multihreading, some parts of the processor must be duplicated for every thread: the register set, the program counter and the instruction window. To manage these instruction windows where fetched instructions are buffered and to decide which instruction from which thread should be issued to which pipeline, a further pipeline stage is added, the Real-TimeIssue(RTI)stage. Special attention demands the fetch stage, which is in charge of preventing the lower priority threads from delaying the hard real-time capable HPT. The same reason applies to the memory controller that should issue memory accesses in the same prioritised order like the RTI issues instructions. The other pipeline stages remain unchanged, besides an additional signal that passes the thread number through the pipeline, in order that the write back stage writes to the appropriate register file. Fig. 1 shows the resulting architecture. ��
Page 2 and 3: Lecture Notes in Computer Science 5
Page 4 and 5: Volume Editors Christian Müller-Sc
Page 6 and 7: General Chair Organization Christia
Page 8 and 9: Organization IX Hartmut Schmeck Kar
Page 10 and 11: Keynote Table of Contents HyVM - Hy
Page 12 and 13: Table of Contents XIII JetBench:AnO
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Exploiting Inactive Rename Slots fo
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128 M. Kayaalp et al. In a supersca
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130 M. Kayaalp et al. INSTRUCTION 1
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132 M. Kayaalp et al. time. Alterna
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134 M. Kayaalp et al. Fig. 3. Numbe
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136 M. Kayaalp et al. The results o
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Efficient Transaction Nesting in Ha
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140 Y. Liu et al. HTMs include TCC
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142 Y. Liu et al. rollback T0 begin
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144 Y. Liu et al. Processor core Pr
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146 Y. Liu et al. 5.2 Results and A
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148 Y. Liu et al. decreases, partia
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Decentralized Energy-Management to
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EnergySaving Cluster Roll: Power Sa
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Effect of the Degree of Neighborhoo
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A Tightly Coupled Accelerator Infra
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232 F. Nowak and R. Buchty 5.3 Comp
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Optimizing Stencil Application on M
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236 F. Xudong et al. compared to th
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238 F. Xudong et al. stencil comput
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244 F. Xudong et al. 5 Related Work
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Abdullah, Tariq 174 Alima, Luc Onan
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