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210 R. Plyaskin and A. Herkersdorf References 1. Agostini, L.V., Silva, I.S., Bampi, S.: Pipelined Fast 2-D DCT Architecture for JPEG Image Compression. In: SBCCI 2001: Proceedings of the 14th symposium on Integrated circuits and systems design, Washington, DC, USA, p. 226. IEEE Computer Society, Los Alamitos (2001) 2. Benini, L., Bertozzi, D., Bogliolo, A., Menichelli, F., Olivieri, M.: MPARM: Exploring the Multi-Processor SoC Design Space with SystemC. J. VLSI Signal Process. Syst. 41(2), 169–182 (2005) 3. Embedded JPEG Codec Library, http://sourceforge.net/projects/mbjpeg 4. Formaggio, L., Fummi, F., Pravadelli, G.: A Timing-Accurate HW/SW Co- Simulation of an ISS with SystemC. In: International Conference on Hardware/Software Codesign and System Synthesis, CODES + ISSS 2004, pp. 152–157 (2004) 5. Guthaus, M., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Brown, R.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: Workload Characterization, Annual IEEE International Workshop, pp. 3–14 (2001) 6. Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R., Meyr, H.: A SW Performance Estimation Framework for Early System-Level-Design Using Fine- Grained Instrumentation. In: DATE 2006: Proceedings of the conference on Design, automation and test in Europe, Leuven, Belgium, pp. 468–473. European Design and Automation Association (2006) 7. Lahiri, K., Raghunathan, A., Dey, S.: System-Level Performance Analysis for Designing On-Chip Communication Architectures. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems 20(6), 768–783 (2001) 8. Lieverse, P., Stefanov, T., van der Wolf, P., Deprettere, E.: System Level Design with Spade: An M-JPEG Case Study. In: IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001, pp. 31–38 (2001) 9. Mahadevan, S., Angiolini, F., Sparso, J., Benini, L., Madsen, J.: A Reactive and Cycle-True IP Emulator for MPSoC Exploration. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems 27(1), 109–122 (2008) 10. Pimentel, A.D., Thompson, M., Polstra, S., Erbas, C.: Calibration of Abstract Performance Models for System-Level Design Space Exploration. J. Signal Process. Syst. 50(2), 99–114 (2008) 11. Prete, C.A., Prina, G., Ricciardi, L.: A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 6(9), 915–929 (1995) 12. Schnerr, J., Bringmann, O., Viehl, A., Rosenstiel, W.: High-Performance Timing Simulation of Embedded Software. In: DAC 2008: Proceedings of the 45th annual Design Automation Conference, pp. 290–295. ACM, New York (2008) 13. Sherman, S.W., Browne, J.C.: Trace Driven Modeling: Review and Overview. In: ANSS 1973: Proceedings of the 1st symposium on Simulation of computer systems, pp. 200–207. IEEE Press, Los Alamitos (1973) 14. VaST Systems Technology, http://www.vastsystems.com 15. Wild, T., Herkersdorf, A., Lee, G.-Y.: TAPES – Trace-Based Architecture Performance Evaluation with SystemC. Design Automation for Embedded Systems 10(2-3), 157–179 (2005)
JetBench: An Open Source Real-Time Multiprocessor Benchmark Muhammad Yasir Qadri 1 , Dorian Matichard 2 , and Klaus D. McDonald Maier 1 1 School of Computer Science and Electronic Engineering University of Essex, CO4 3SQ, UK yasirqadri@acm.org, kdm@essex.ac.uk 2 Ecole Nationale d’Electronique, Informatique et Radiocommunications de Bordeaux, ENSEIRB matichar@enseirb.fr Abstract. Performance comparison among various architectures is generally attained by using standard benchmark tools. This paper presents JetBench, an Open Source OpenMP based multicore benchmark application that could be used to analyse real time performance of a specific target platform. The application is designed to be platform independent by avoiding target specific libraries and hardware counters and timers. JetBench uses jet engine parameters and thermodynamic equations presented in the NASA’s EngineSim program, and emulates a real-time jet engine performance calculator. The user is allowed to determine a flight profile with timing constraints, and adjust the number of threads. This paper discusses the structure of the application, thread distribution and its scalability on a custom symmetric multicore platform based on a cycle accurate full system simulator. Keywords: Real-time, Multiprocessor, Application Benchmark. 1 Introduction Benchmarks are generally classified into two types, i.e. 1) synthetic benchmarks and 2) application benchmarks. Synthetic benchmarks are designed to exploit particular property of a processor such as instruction per second (IPS), cache performance, I/O bandwidth etc, whereas application benchmarks are centred towards one particular application such as automotive, office automation, etc. The concept of using benchmarks for performance characterization of the system is common practice and some processor manufacturers have proposed their own benchmarks [1]. However such benchmarks strive to give better performance on a particular platform, third party benchmarks are a good way to compare the performance amongst various architectures impartially and transparently. The JetBench benchmark presented in this paper is an application benchmark written in C, for real-time jet engines thermodynamic calculations. It is a multithreaded application for shared memory architectures. The benchmark is based on OpenMP [2], and could be seamlessly ported to any platform supporting it. The benchmark provides user the flexibility to specify custom workload, that could be a real flight C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 211–221, 2010. © Springer-Verlag Berlin Heidelberg 2010
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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