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206 R. Plyaskin and A. Herkersdorf 4.1 Accuracy of Generated Traces In order to evaluate accuracy of the proposed trace generation method and to estimate a possible gain in simulation performance compared to the cycle accurate simulator, we took a set of five benchmarks. Each benchmark represented a particular application domain. In jpeg benchmark, the application performed encoding of a bitmap image into the JPEG format [3]. Additionally, we selected bitcount, FFT, stringsearch, andsha benchmarks from MiBench suite [5] that represent correspondingly Automotive, Telecommunications, Office, and Security application categories. The experiments were conducted on a PC with a 2 GHz Intel Core 2 Duo processor and 1 GB of RAM. During the tests we used the following input data for the applications: – Jpeg: a test bitmap image of size 104×72 pixels; – FFT : polynomial function with one random sinusoid and 512 samples; – Bitcount: 50000 iterations; – Sha: the small ASCII text file provided with the benchmark; – Stringsearch: the large string provided with the benchmark. The cross-compiled C-code of each application was executed on a CoMET virtual platform. The SoC architecture modeled in the tool consisted of a PowerPC e200z6 CPU with a 32 kB write-back cache, a generic memory model with an access latency of 1 cycle, and a generic model of a bus with a request latency of 1 cycle. The resultant log was further processed by the trace generator which produced a trace file for each benchmark code. In the next step, we executed the generated traces in the trace simulator (TS) containing the same SoC components as in the CoMET virtual platform. Parameters of the abstracted modules, e.g. the memory and bus latencies as well as the cache size, were adjusted to the parameters of the CoMET modules. Clock frequencies of the components both in CoMET and TS were set to 100 MHz. Results of the estimated execution time for each benchmark are given in Table 1. Although the trace simulator does not have a notion of instructions, the simulation performance in MIPS was calculated as the number of instructions of the corresponding application divided by the time of the trace simulation. We refer to the simulation time as a real time elapsed from the start to the end of Table 1. Comparison of VaST CoMET and trace-based simulations Benchmark Number of instructions Simulation Estimated cycles performance, MIPS VaST TS Error,% VaST TS Speedup VaST perf. with trace gen., MIPS stringsearch 1.68M 2.86M 2.93M 2.18 7.01 11.97 1.71 0.94 jpeg 3.01M 5.18M 5.16M -0.37 6.52 25.07 3.84 0.98 sha 10.81M 12.8M 12.45M -2.77 54.60 72.07 1.32 1.18 FFT 21.68M 27.23M 25.96M -4.67 28.64 60.23 2.10 1.00 bitcount 34.18M 43.16M 42.71M -1.04 90.17 126.57 1.40 1.40
A Method for Accurate High-Level Performance Evaluation 207 the simulation. This time does not include the initialization phase of the simulation, in which the components’ models are instantiated. The initialization phase in VaST CoMET was approximately measured to be 5 s. In contrast, due to the higher abstraction level of the components, the initialization in the trace simulator took 0.03 s. Small initialization times may be desirable when several simulations have to be performed iteratively. The performance of VaST simulations given in the table was measured without generation of traces. With the enabled trace generation, the simulator’s performance was reduced to 0.94–1.4 MIPS due to the overhead associated with creating the trace files. The errors in the trace-based simulation originate from the simplified memory access mechanisms. First, during the trace generation the actual timing of the read/write primitives is considered to be 1 cycle in case of cache hits. In fact, the execution of the corresponding load/store instructions can take more than one cycle, e.g., due to possible pipeline stalls. In the trace simulation, these effects are omitted and, thus, the execution time is underestimated. Second, on cache misses the CPU model issues blocking transactions to the memory. However, in reality the CPU would continue executing next instructions until it stalls due to the data dependencies of the upcoming instruction. Therefore, the executed time becomes overestimated. The overall error produced by the trace simulation is a superposition of these two effects. If higher simulation accuracy is required, the trace generation method has to be correspondingly modified with a consideration of possible data dependencies inside delay primitives. 4.2 Design Space Exploration In order to demonstrate the presented workflow during high-level explorations of MPSoC architectures, we selected the jpeg application as a simplified but representative example. As one of many possible architectural solutions, the application can be executed on a symmetric multi-processor platform, in which each CPU performs processing of a particular fragment of the picture. On an architecture with multiple CPUs that share common resources, the execution time of the application will be altered due to additional contention periods. In order to study this effect in the trace simulator, we modeled a sample architecture consisting of 4 CPUs, a common arbitrated bus and a shared memory. Since each CPU should process an individual block of data, we generated 4 different traces. Each trace represented the processing of an image block of size 128×128 pixels. The traces were executed in parallel without any data dependencies between them. Table 2 presents results of the application’s profiling in the trace simulator. As can be concluded from the experiment, the most performance demanding subroutine was a calculation of the discrete cosine transform (dct). As a possible solution during the design space exploration, this function can be offloaded to a hardware accelerator attached to the peripheral bus (Fig. 5). The discrete cosine transform is performed on an image block of size 8×8 pixels resulting in data transfers of 64 bytes to the accelerator. In order to enable the hardware acceleration, we replaced every part of the traces representing the execution of
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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130 M. Kayaalp et al. INSTRUCTION 1
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