Architecture of Computing Systems (Lecture Notes in Computer ...

A Method for Accurate High-Level Performance Evaluation 203
the impact of shared resources on performance of the application. In addition,
the simulator can profile the application traces allowing the designer to identify
possible options for HW/SW functional repartitioning. The repartitioning can
be performed by a simple trace modification and analyzed in the simulator in
an iterative manner. The following sections provide further details on each step
of the proposed workflow.
3.1 Generation of Traces
In order to estimate the execution time of the target software, cycle accurate
CPU simulators typically contain models of micro-architectural components,
e.g., branch predictors or instruction pipelines. Using a CPU simulator, the
designer can observe the contents of CPU’s internal registers and memory addresses
in load and store instructions. For the generation of traces, the order of
the instructions as well as their timing information is of the most importance.
In a cycle accurate simulation, the executed instructions can be categorized
into two types:
– Processing instructions not resulting in a request on the bus;
– Communication instructions that perform load and store operations.
Since none of the processing instructions initiates memory accesses, a group
of subsequent processing instructions are translated to a DELAY trace primitive
(Fig. 3). The trace generator calculates the overall execution time of this group
and stores it as a parameter of the primitive. Correspondingly, the communication
instructions are translated to READ and WRITE trace primitives. Information
on the destination target of each transaction and the target memory address is
stored as primitive’s parameters as well.
In order to enable profiling of the application trace, trace primitives are divided
into groups. Each group represents an execution of the instructions within
a particular subroutine of the target SW code. For each group, the trace generator
identifies the subroutines’ names using the symbol table of the target code
Fig. 3. Generation of traces using a log file from a CPU cycle accurate simulation