Architecture of Computing Systems (Lecture Notes in Computer ...

Autonomic Workload Management
for Multi-core Processor Systems
Johannes Zeppenfeld and Andreas Herkersdorf
Technische Universität München
{zeppenfe,herkersdorf}@tum.de
Abstract. This paper presents the use of decentralized self-organization concepts
for the efficient dynamic parameterization of hardware components and
the autonomic distribution of tasks in a symmetrical multi-core processor
system. Using results obtained with an autonomic system on chip simulation
model, we show that Learning Classifier Tables, a simplified XCS-based
reinforcement learning technique optimized for a low-overhead hardware implementation
and integration, achieves nearly optimal results for dynamic workload
balancing during run time for a standard networking application at task
level. Further investigations show the quantitative differences in optimization
quality between scenarios when local and global system information is included
in the classifier rules. Autonomic workload management or task repartitioning
at run time relieves the software application developers from exploring this NPhard
problem during design time, and is able to react to dynamic changes in the
MP-SoC operating environment.
1 Introduction
1.1 Multi-core Processing
Single-chip multi-processors became the mainstream architecture template for advanced
microprocessor designs across a wide spectrum of application domains. Intel,
the market leader for general purpose computing, abandoned its traditional strategy to
primarily scale microprocessor performance through continued increase in core clock
frequency and introduced parallel dual-, quad- and recently octal-core (Nehalem)
Xeon processors [1] instead. In their research labs, Intel integrated the 80 core Tera-
Scale processor [2] with a 2D network on chip and sophisticated 3D memory stack
access. SUN Niagara, ARM MPCore, IBM Cell Broadband Engine, Nvidia GeForce,
the CSX700 from ClearSpeed, and the TILE64 from Tilera are other examples of a
non-exhaustive list of massively parallel multi-core architectures for use in mobile
communications, graphics processing, gaming, industrial automation and highperformance
scientific computing. While progress in deep sub-micron CMOS technology
integration enabled the physical realization of this vast amount of nominal
processing capacity on a single chip, the application programmer community – across
all of the above mentioned systems – is minimally supported by tools and methods to
efficiently exploit the available parallel resources [3]. We regard this circumstance a
major challenge for a fast and efficient adoption of multi-core processors.
C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 49–60, 2010.
© Springer-Verlag Berlin Heidelberg 2010