Architecture of Computing Systems (Lecture Notes in Computer ...

Recommendations

Info

128 M. Kayaalp et al. In a superscalar processor, the rename table has multiple ports to allow the renaming of multiple instructions per cycle. Every instruction that is renamed together in the same cycle needs to acquire a free register from the free list, update the rename table and read the mappings for its source operands concurrently. Since some of the instructions that are renamed in the same cycle are dependent on each other with WAR or WAW hazards, instructions may try to write to the same entry of the rename table in the same cycle or an instruction may need to wait for a previous instruction to update the rename table before it can read the mappings for its source operands. This kind of sequential access to the rename table may either increase the cycle time or may not be even possible due to some design choices. Therefore register renaming stage of the pipeline includes a dependency checking logic to detect intragroup dependencies. INSTRUCTION 1 Destination Source-1 Source-2 C1 C2 C3 = = = C6 INSTRUCTION 2 Destination Source-1 Source-2 C4 C5 = = = Fig. 1. Comparison circuitry of the rename logic INSTRUCTION 3 Destination Source-1 Source-2 Fig. 1 shows the structure of the dependency checking logic for a machine that renames 3 instructions concurrently. There are multiple comparator circuits that compare the destination and source tags of all concurrently renamed instructions. Each instruction’s destination architectural register tag is compared to the source operand and destination tags of all of the subsequent instructions. In case of a match, the physical register mapping corresponding to the source operand of the subsequent instruction is obtained from the destination physical register field of the preceding instruction rather than being read from the rename table. This way a serial write and read operation is avoided. Similarly, in order to avoid updating the same rename table entry multiple times in a single cycle, destinations of all of the instructions are compared against each other. If a match is detected, only the youngest instruction is allowed to update the rename table. The match/mismatch signals that are produced by the comparators C1…C9 are fed into the priority decoders to control the access of the instructions to the mapping table. C7 C8 C9 = = =
Exploiting Inactive Rename Slots for Detecting Soft Errors 129 3 Using Dependency Checking Logic for Soft Error Detection Although superscalar processors are designed for high throughput, pipeline width is not fully used from time to time. As the pipeline of the processor is not filled with instructions to its capacity, the number of simultaneously renamed instructions is reduced. This fact was previously observed by Moshovos and was exploited to reduce the complexity and the power dissipation of the rename table [9]. When the number of concurrently renamed instructions is below the processor rename width, dependency checking logic of the rename stage is not employed to its capacity. The comparators that are wired to the empty instruction slots during this period stay idle and generally are not used for any purpose. Therefore during the times when the processor is not using all of its rename slots, these comparators can be used to detect soft errors that occur on the register tags of the instructions when they are passing through the frontend of the processor. Value replication is a long time known and used technique for reliability. Although it is possible to detect single bit errors in a value by adding a single parity bit, replicating the value can detect and possibly correct multiple errors if there are enough copies of the value. Errors can be detected with one redundant copy of a value and can be corrected with two redundant copies through simple voting [2]. More than three copies of the same data leads to a stronger protection as there will be more chances to recover from an error. Instruction replication was proposed and implemented in different ways to cope with soft errors in the past. Redundant multithreading was proposed to replicate the whole thread running on the processor to detect any soft errors [11][13][19]. While it offers a system level protection, replicating each and every instruction in a program results in some performance degradation as processor resources are divided into two to execute instructions from both the leading and the trailing threads. Selectively replicating most vulnerable instructions and processor structures have been proposed as a good tradeoff between performance degradation and fault coverage. However, most of the previous approaches have concentrated on protecting the backend structures of the processor such as the functional units, the issue queue or the reorder buffer [2][7][18]. In this paper we propose to replicate the register tags of the instructions into the register tag fields of the unused instruction slots and use the idle comparators of the dependency checking logic to detect and correct soft errors that occur in the frontend of the processor. 3.1 Protecting the Tags of a Single Instruction When there is only one instruction flowing through the pipeline, all of the hardware resources can be used for this single instruction. It is possible to detect the errors on both the source tags and destination register identifier if the pipeline width is at least 4, without adding any additional comparator circuit. In order to maximize the error coverage, the tags of the single running instruction is copied to the empty fields of the unused slots as shown in Fig. 2 as early as possible in the pipeline. This copy operation is mostly likely to happen when the instruction is decoded. Also the copies may be ready right after fetching if a trace cache, where decoded instances of the
Page 2 and 3:
Lecture Notes in Computer Science 5
Page 4 and 5:
Volume Editors Christian Müller-Sc
Page 6 and 7:
General Chair Organization Christia
Page 8 and 9:
Organization IX Hartmut Schmeck Kar
Page 10 and 11:
Keynote Table of Contents HyVM - Hy
Page 12 and 13:
Table of Contents XIII JetBench:AnO
Page 14 and 15:
How to Enhance a Superscalar Proces
Page 16 and 17:
4 J. Mische et al. The Real-time Vi
Page 18 and 19:
6 J. Mische et al. 4.1 Instruction
Page 20 and 21:
8 J. Mische et al. Additionally the
Page 22 and 23:
10 J. Mische et al. % of unused pip
Page 24 and 25:
12 J. Mische et al. % of cycles spe
Page 26 and 27:
14 J. Mische et al. 16. Lickly, B.,
Page 28 and 29:
16 G. Aşılıoğlu, E.M. Kaya, and
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
26 T.B. Preußer, P. Reichel, and R
Page 40 and 41:
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
38 P. Bellasi, W. Fornaciari, and D
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 62 and 63:
50 J. Zeppenfeld and A. Herkersdorf
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
62 B. Jakimovski, B. Meyer, and E.
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
74 M. Bonn and H. Schmeck Fig. 1. J
Page 88 and 89:
76 M. Bonn and H. Schmeck 2.2 Node
Page 90 and 91: 78 M. Bonn and H. Schmeck Uptime-ba
Page 92 and 93: 80 M. Bonn and H. Schmeck 2.4 Simul
Page 94 and 95: 82 M. Bonn and H. Schmeck done rate
Page 96 and 97: 84 M. Bonn and H. Schmeck Fig. 8. J
Page 98 and 99: 86 M. Bonn and H. Schmeck tells the
Page 100 and 101: 88 J.-P. Steghöfer et al. � �
Page 102 and 103: 90 J.-P. Steghöfer et al. mechanis
Page 104 and 105: 92 J.-P. Steghöfer et al. resource
Page 106 and 107: 94 J.-P. Steghöfer et al. Choose a
Page 108 and 109: 96 J.-P. Steghöfer et al. 1. Defin
Page 110 and 111: 98 J.-P. Steghöfer et al. and all
Page 112 and 113: 100 J.-P. Steghöfer et al. 19. Kim
Page 114 and 115: 102 K. Kloch et al. large-scale sys
Page 116 and 117: 104 K. Kloch et al. a�t� 1.0 0.
Page 118 and 119: 106 K. Kloch et al. constant. This
Page 120 and 121: 108 K. Kloch et al. Relative number
Page 122 and 123: 110 K. Kloch et al. (a) infection r
Page 124 and 125: 112 K. Kloch et al. (ii) Phase of a
Page 126 and 127: 114 P. Petoumenos et al. Studying t
Page 128 and 129: 116 P. Petoumenos et al. % of Misse
Page 130 and 131: 118 P. Petoumenos et al. IQ: n 4-in
Page 132 and 133: 120 P. Petoumenos et al. downsizing
Page 134 and 135: 122 P. Petoumenos et al. As long as
Page 136 and 137: 124 P. Petoumenos et al. comparable
Page 138 and 139: Exploiting Inactive Rename Slots fo
Page 142 and 143: 130 M. Kayaalp et al. INSTRUCTION 1
Page 144 and 145: 132 M. Kayaalp et al. time. Alterna
Page 146 and 147: 134 M. Kayaalp et al. Fig. 3. Numbe
Page 148 and 149: 136 M. Kayaalp et al. The results o
Page 150 and 151: Efficient Transaction Nesting in Ha
Page 152 and 153: 140 Y. Liu et al. HTMs include TCC
Page 154 and 155: 142 Y. Liu et al. rollback T0 begin
Page 156 and 157: 144 Y. Liu et al. Processor core Pr
Page 158 and 159: 146 Y. Liu et al. 5.2 Results and A
Page 160 and 161: 148 Y. Liu et al. decreases, partia
Page 162 and 163: Decentralized Energy-Management to
Page 164 and 165: 152 B. Becker et al. Furthermore, t
Page 166 and 167: 154 B. Becker et al. An optimizing
Page 168 and 169: 156 B. Becker et al. smart-home man
Page 170 and 171: 158 B. Becker et al. freedom like w
Page 172 and 173: 160 B. Becker et al. Power [W] 4500
Page 174 and 175: EnergySaving Cluster Roll: Power Sa
Page 176 and 177: 164 M.F. Dolz et al. Themodulequeri
Page 178 and 179: 166 M.F. Dolz et al. This daemon al
Page 180 and 181: 168 M.F. Dolz et al. been submitted
Page 182 and 183: 170 M.F. Dolz et al. On the other h
Page 184 and 185: 172 M.F. Dolz et al. at the inactiv
Page 186 and 187: Effect of the Degree of Neighborhoo
Page 188 and 189: 176 T. Abdullah et al. A zone based
Page 190 and 191:
178 T. Abdullah et al. A consumer/p
Page 192 and 193:
180 T. Abdullah et al. Messages 140
Page 194 and 195:
182 T. Abdullah et al. (except when
Page 196 and 197:
184 T. Abdullah et al. % Matchmakin
Page 198 and 199:
186 T. Abdullah et al. show that th
Page 200 and 201:
188 M. Schindewolf, D. Kramer, and
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
200 R. Plyaskin and A. Herkersdorf
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
212 M.Y. Qadri, D. Matichard, and K
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
A Tightly Coupled Accelerator Infra
Page 236 and 237:
224 F. Nowak and R. Buchty where A
Page 238 and 239:
226 F. Nowak and R. Buchty Fig. 3.
Page 240 and 241:
228 F. Nowak and R. Buchty Table 2.
Page 242 and 243:
230 F. Nowak and R. Buchty Table 4.
Page 244 and 245:
232 F. Nowak and R. Buchty 5.3 Comp
Page 246 and 247:
Optimizing Stencil Application on M
Page 248 and 249:
236 F. Xudong et al. compared to th
Page 250 and 251:
238 F. Xudong et al. stencil comput
Page 252 and 253:
240 F. Xudong et al. threads in the
Page 254 and 255:
242 F. Xudong et al. Speedup 14 12
Page 256 and 257:
244 F. Xudong et al. 5 Related Work
Page 258:
Abdullah, Tariq 174 Alima, Luc Onan
show all

Architecture of Computing Systems (Lecture Notes in Computer ...

Create successful ePaper yourself

Delete template?

Save as template?