Architecture of Computing Systems (Lecture Notes in Computer ...

threads ALUTs regs MHz
1 14808 3857 27.17
2 21129 5968 26.10
3 27519 8061 24.38
4 31603 10125 17.55
5 39325 12195 11.10
6 45400 14271 8.52
7 49082 16378 7.00
How to Enhance a Superscalar Processor 9
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#threads
Fig. 2. CarCore hardware characteristics depending on the number of threads
sent some cycles earlier in order that the second microinstruction arrives at the
write back stage at the same cycle as the data arrives from memory.
To avoid the restriction of the other threads, not to issue memory operations,
Address Buffers are added. There is one address buffer per thread located in
the memory controller. After a store or the first microinstruction of a load the
thread is temporarily suspended from further issuing instructions. When the
memory instruction arrives at the memory controller the address is saved in
the address buffer of the appropriate thread. Whenever a memory operation is
completed, the memory controller looks at the address buffers in priority order
and starts a new memory operation if there is a valid entry. At the same cycle the
memory controller notifies the RTI to resume issuing instructions of the thread
whose data word had just arrived. Depending on the kind of instruction the RTI
continues with the second microinstruction of a load or the next instruction after
astore.
There is another advantage of the Split Phase Load / Address Buffer technique:
the memory latency can vary and there is no upper bound. If the memory
access is fast, the second microinstruction of the load is issued earlier, if it
takes longer, the second microinstruction (respectively the next instruction after
a store) is issued later. So multiple memories with different access times are
supported.
5 Evaluation
We started our SMT enhancement with a singlethreaded SystemC model of
the CarCore and enhanced it to support multithreading. The final SystemC
model was translated to VHDL for FPGA synthesis. There are separate data and
instruction memory buses, each 64 bits wide. In the FPGA model the memory
latencies are fixed to 0 for the instruction memory (internal on-chip RAM) and
4 cycles to the off-chip data memory.
Fig. 2 shows the size of the CarCore on an Altera Stratix II EP2S180F1020C3
device. The numbers of Adaptive Lookup Tables (ALUTs) and register bits
grow nearly linear with the number of threads. Each thread requires about 6000
ALUTs and 2000 registers and the base processor adds about 9000 ALUTs and
2000 registers.
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