Architecture of Computing Systems (Lecture Notes in Computer ...

132 M. Kayaalp et al.
time. Alternatively we can copy the destination tag of one of the instructions to the
source tag fields of instruction 3 and one source tag of the same instruction both to the
destination tag of the third instruction and the source tags of the fourth instruction
slot. This way it is possible to protect the destination tag and one of the source tags of
one of the instructions.
3.3 Renaming More Than 2 Instructions Simultaneously
Our proposed technique can also provide partial soft error detection coverage if three
instructions are renamed simultaneously. In this case only an error on the destination
tag of one of the instructions can be detected by copying this tag to all of the fields
(destination + sources) of the fourth instruction slot. In a 4-wide processor, the proposed
technique won’t be able to provide any soft error detection coverage since there
won’t be any empty slots or idle comparators.
3.4 Using the Bubbles in the Pipeline to Improve Soft Error Coverage
Our proposed scheme cannot offer any soft error detection coverage if the pipeline is
fully employed. Also when there are more than one instruction flowing through the
pipeline there are not enough storage slots to cover all of the source and destination
tags. However the processor pipeline is occasionally not fully employed which offers
a whole set of resources to check tags of one instruction. It is possible to copy the tag
information of an instruction to a following empty stage to achieve error coverage. In
this case there are different options that a designer may choose:
1. One of the instructions (the instruction that is the last in program order) falls behind
to the previous stage where it can replicate all of its tags into the storage space
for full soft error coverage. This solution may introduce a delay penalty as the instruction
that falls back is delayed inside the pipeline, which will delay its entrance
to the issue queue and may delay its issue to the function units. We evaluated this
scheme but interestingly the soft error vulnerability increased while the performance
dropped.
2. Tags of one of the instructions are copied to the next cycle and when these bogus
tags arrive at the rename stage, they are compared against the original tag by holding
onto this tag in the rename stage. This solution does not result in performance
degradation but requires some hardware support. In this work we used this scheme.
3. All of the instructions copy their tags to the empty slot in the previous stage. However
in this case there should be a hardware design that supports the checking of
tags between stages. This may be accomplished by copying the entire stage and
checking the outcomes of all comparators by latching the comparison outcomes.
This mandates the use of a single-bit flip-flop (or a latch) for storing the outcomes
of all comparators at the rename stage and an extra comparator should be employed
to compare the contents of the latches with the outcomes of the comparators. In the
examples depicted in Fig. 1 and Fig. 2 there are 9 comparators which means that
there will be a 9 bit comparison outcome signature. If this outcome is latched and
compared against the 9 bit comparator outcome signature of the replicated bogus
tags in the next cycle any mismatch would mean a soft error. Therefore it is possible
to protect the entire group of tags by using 9 latches and one 9 bit comparator.
Note that this scheme shows an error if there is a mismatch in the signatures but a