Architecture of Computing Systems (Lecture Notes in Computer ...

22 G. Aşılıoğlu, E.M. Kaya, and O. Ergin
The head pointers of each FIFO queues are also separate registers that are updated
from the commit stage of the pipeline. When an instruction is committed and removed
from the reorder buffer it simply increments the head pointer of its destination architectural
register. Note that instructions do not access the payload area from the commit
stage but they only access the head pointer register.
Processor is stalled at the rename stage if the contents of the head pointer register
is just one over the contents of the tail pointer register for an architectural register that
needs to be renamed. Since these registers are just incremented unless there is an
exception (such as a branch misprediction), they are better be implemented as a
counter with parallel data loading capability.
The checkpoint table that is needed to recover the contents of the pointer register in
case of an exception or misprediction is a plain payload structure that only holds the
values of the registers just at the time a branch reaches the rename stage. That structure
is implemented by using SRAM bitcells and it is smaller than a register file
which makes it possible to access this structure in less than a cycle.
Complexity is moved to the pointer registers in the proposed scheme since these
registers are actually counters but they also need a logic for immediate data loading
and comparison of head and tail pointers. There is also a control logic that allows the
reading and writing of values by using only the contents of the tail pointer.
7 Results and Discussions
In order to get an accurate idea of the performance impact of the proposed technique
we used the PTLsim simulator [8] that is capable of simulating x86 instructions. We
ran the spec 2000 benchmarks for 1 billion committed instructions. Table 1 shows the
simulated processor configuration.
The simulation was run with checkpointing and walk-backwards recovery mechanisms
already included in PTLsim. The FIFO tests were based on a modification of
the checkpointing algorithm which imposed penalties to the cycle count of the simulation
when the allocated queue was filled, and performed similar to checkpointing
when the queues had available space.
Table 1. Simulation Parameters
Parameter Configuration
Machine width 4-wide fetch, 4-wide issue, 4-wide commit
Window size 32 entry issue queue, 48 entry load queue, 32 entry store queue, 128–
entry ROB
Function Units Integer ALU (2), Load unit (2),
FPU (2), Store Unit (2)
Latencies
Integer ALU (1), ALU Multiplication (4), ALU Bit scans(3), ALU
Division (32), FPU Arithmetic (6), FPU Vector Arithmetic (1)
L1 I-Cache 32 KB, 4-way set-associative, 64 byte line, 1 cycle hit time
L1 D-Cache 16 KB, 4–way set–associative, 64 byte line, 1 cycle hit time
L2 Unified Cache
256 KB , 16–way set–associative, 64 byte line, 6 cycles hit time
L3 Unified Cache
4 MB, 32–way set–associative, 64 byte line, 16 cycles hit time
Branch Predictor Meta predictor using bimodal and two-way
Memory 140 cycles hit time