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Architecture of Computing Systems (Lecture Notes in Computer ...

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Hierarchical Distributed Control <strong>of</strong> Power and Performances 41<br />

Operat<strong>in</strong>g System<br />

Abstraction Layer<br />

User−space<br />

Key:<br />

Local Optimization<br />

policies<br />

Optimal System−Wide<br />

Configuration<br />

Global Optimization<br />

policies<br />

Optimization<br />

Layer<br />

QoS<br />

Requirements<br />

Resource<br />

Manager<br />

Devices<br />

Drivers Platform Code<br />

Work<strong>in</strong>g<br />

Region<br />

FSC<br />

Model Layer<br />

Silicon and Architectural<br />

mechanisms<br />

PSM<br />

ASM<br />

CPM Core:<br />

− FSC Identification<br />

− FSC Order<strong>in</strong>g<br />

− FSC Selection<br />

Tasks<br />

abstraction/modell<strong>in</strong>g piece <strong>of</strong> <strong>in</strong>formation device or tool flow <strong>of</strong> <strong>in</strong>formation<br />

Fig. 2. A real comput<strong>in</strong>g system, with many different devices and applications, is<br />

so complex that it is not convenient to model all this complexity <strong>in</strong> order to solve<br />

the consumption and performances optimization problem. Therefore we perform an<br />

abstraction and model<strong>in</strong>g to properly support the optimization technique.<br />

the framework to consider target system details (e.g., devices dependencies).<br />

F<strong>in</strong>ally, each device <strong>in</strong> the system is described with<strong>in</strong> the model by a set <strong>of</strong><br />

“Device Work<strong>in</strong>g Region” (DWR). A device generally can have different WMs,<br />

which correspond to different resources usage and supported QoS. WMs could<br />

be as simple as ’device on’ and ’device <strong>of</strong>f’, or even more complex such as all the<br />

different operat<strong>in</strong>g frequencies <strong>of</strong> a CPU or the different connection protocols<br />

supported by a 3G modem. What exactly are the WMs <strong>of</strong> a device is def<strong>in</strong>ed by<br />

the correspond<strong>in</strong>g driver. Thus, a DWR is an abstract representation <strong>of</strong> a device<br />

WM and it is def<strong>in</strong>ed by a set <strong>of</strong> ranges on each SWM which is sensible for the<br />

considered device. A device is “sensible” to a SWM if any change <strong>of</strong> its value<br />

can imply a reconfiguration <strong>of</strong> the device and vice versa. In <strong>in</strong>stance, a DVFS<br />

driver for the control <strong>of</strong> the processor clock frequency is sensible to a SWM like<br />

’CPU Frequency’.<br />

The Model Layer takes as <strong>in</strong>put the <strong>in</strong>formation represent<strong>in</strong>g the system resources<br />

and capabilities, exploit<strong>in</strong>g the abstraction def<strong>in</strong>ed <strong>in</strong> the lower layer,<br />

and generates as output an architecture <strong>in</strong>dependent representation <strong>of</strong> all the

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