Architecture of Computing Systems (Lecture Notes in Computer ...

Efficient Transaction Nesting in Hardware Transactional Memory 139
programming models, transactional memory can improve the programmability,
avoid deadlock and furthermore, promote performance of concurrent programs.
Transaction nesting is one of the ongoing challenges for hardware transactional
memory. To support efficient closed nesting, this paper proposes a conditional
partial rollback (CPR) scheme which supports partial rollback conditionally
without increasing hardware complexities significantly. Compared to the
flattening model which is commonly-used in hardware transactional memory, the
CPR scheme rolls back to the conflicted transaction itself or one of its outer-level
transactions instead of the outermost if given conditions are satisfied. Transactional
memory system architecture with support of the CPR scheme is also
proposed based on multi-core processor and current cache coherent mechanisms.
The system has been implemented by simulation. Its performance is evaluated
by seven benchmark applications. Evaluation results show that the CPR scheme
outperforms flattening model in performance and scalability.
The rest of this paper is organized as follows. Section 2 gives an overview of
transactional memory. Section 3 discusses transaction nesting models and presents
the CPR scheme which supports conditional partial rollback. Section 4 introduces
the architecture of our hardware transactional memory. Section 5 evaluates the
system with benchmark applications. And Section 6 concludes the paper.
2 Overview of Transactional Memory and Related Work
The concept of transactional memory is first proposed in [1]. It defines transaction
as a sequence of instructions which is executed atomically, that is, a transactions is
executed either completely (committed) or has no effect (aborted). The atomicity
of a transaction is supported at the architecture level, either in hardware or software.
During the execution of a transaction, all the modifications to the data are
buffered and invisible to the system, if a conflict between two transactions occurs
due to reading or writing to the same data, one of these transactions aborts its
execution and rolls back. The transaction ends up with commit operation, which
makes all the buffered modifications visible to the system.
Compared to traditional lock-based programming model, transactional memory
has a series of advantages: firstly, programmer only need to partition the
transactions without considering synchronization and mutual exclusion among
threads, so the transactional program is easy to write, and programmability is
improved; secondly, the synchronization among transactions is done by the system
automatically, and a transaction can be aborted and rolled back at anytime,
so deadlock can be avoided; and thirdly, multiple transactions can be speculative
executed concurrently, and rollback only occurs on conflict, as the result,
performance of transaction programs can be improved.
According to the implementation styles, current transactional memory system
falls into two categories: hardware transactional memory (HTM) and software
transactional memory (STM). HTM supports atomicity of transactions by hardware,
and achieves high performance at the cost of resource limitations (e.g.
size of a transaction); also the processor architecture must be modified. Typical