Architecture of Computing Systems (Lecture Notes in Computer ...

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232 F. Nowak and R. Buchty 5.3 Comparison In order to evaluate our architecture, we performed 220 multiply-accumulates of the value v =2−20 onto an init value of 220 using our hardware and two software solutions. For the latter, we employed an implementation based on the GNU Multiprecision Library (GMP) using a 256 bits wide internal floating-point representation and one based on C-XSC where a 4288 bits wide fixed-point accumulator is employed. Individual runtimes were measured on an Intel Pentium 4 3,2 GHz over 128 runs. All programs were compiled with -O2. Subtracting the initialization value afterwards we obtained the correct result 2−20 , which fails when using regular double-precision floating-point operations. The measurements can be found in Table 7. We additionally provide the execution time with regular double-precision, which is about 100 times less compared to the highly accurate libraries. Our architecture concept is capable of executing exact multiply-accumulate operations in about the same order of time. Based on the maximum achievable throughput for HT400, we can derive a theoretical maximum speedup of 400 =76.38 over state-of-the-art software im- 5.237 plementations of exact arithmetics. Following Sect. 5.1, limitations of the target 88 platform still allow a maximum speedup of 5.237 =16.80. 6 Results and Future Work As of now, our system allows processing two MAC operation each 3 cycles while running at a frequency of 100 MHz, which leads to a theoretical processing speed of 66M MAC operations per second. Note that these operations are carried out in exact arithmetics, avoiding rounding and windowing errors. We showed in Section 3 how a multitude of accumulation units can help to constantly process streamed data and how using the DDR memory can further speed up the overall performance up to 400 MAC operations per second. A technology scaling showed that this architecture is a viable approach to exploit the available bandwidth of the HyperTransport bus. For better results, the implementation of the accumulator unit will be revised, promising a latency of 1 and even less resource usage. Our future work consists of integrating the DDR memory and DMA controllers in order to carry out detailed measurements with numerical software where computation with exact arithmetics enables solving more complex problems. We also plan to extend our system infrastructure by numerical error measurements so that functions be directed to their exact arithmetics implementation automatically, sacrificing speed over robustness and numerical stability. Similar to [1], the approach will be extended towards microprogramming capabilities so that (parts of) algorithms can be completely loaded onto the accelerator, thus supporting sparse matrix multiplications. Finally, the architecture is designed to deliver coarse-grained function acceleration of numerical algorithms such as the Lanczos algorithm.
References A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics 233 1. Danese,G.,Leporati,F.,Bera,M.,Giachero,M.,Nazzicari,N.,Spelgatti,A.:An Accelerator for Physics Simulations. Computing in Science and Engineering 9(5), 16–25 (2007) 2. Kumar, V.B.Y., Joshi, S., Patkar, S.B., Narayanan, H.: FPGA Based High Performance Double-Precision Matrix Multiplication. In: VLSID 2009: Proceedings of the 2009 22nd International Conference on VLSI Design, Washington, DC, USA, pp. 341–346. IEEE Computer Society, Los Alamitos (2009) 3. DuBois, D., DuBois, A., Boorman, T., Connor, C., Poole, S.: An Implementation of the Conjugate Gradient Algorithm on FPGAs. In: Pocek, K.L., Buell, D.A. (eds.) FCCM, pp. 296–297. IEEE Computer Society, Los Alamitos (2008) 4. Morris, G.: Floating-Point Computations on Reconfigurable Computers. In: HPCMP-UGC ’07: Proceedings of the 2007 DoD High Performance Computing Modernization Program Users Group Conference, Washington, DC, USA, pp. 339– 344. IEEE Computer Society Press, Los Alamitos (2007) 5. Strzodka, R., Göddeke, D.: Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components. In: IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), April 2006, pp. 259–268 (2006) 6. Herbordt, M., Sukhwani, B., Chiu, M., Khan, M.A.: Production Floating Point Applications on FPGAs. In: Symposium on Application Accelerators in High Performance Computing, SAAHPC 2009 (July 2009) 7. Kulisch, U.W.: Complete Interval Arithmetic and Its Implementation on the Computer. In: Cuyt, A., Krämer, W., Luther, W., Markstein, P. (eds.) Numerical Validation in Current Hardware Architectures. LNCS, vol. 5492, pp. 7–26. Springer, Heidelberg (2009) 8. Bierlox, N.: Ein VHDL Koprozessorkern für das exakte Skalarprodukt. PhD thesis, Universität Karlsruhe (November 2002), http://digbib.ubka.uni-karlsruhe.de/volltexte/documents/1053 9. Kirchner, R., Kulisch, U.: Accurate arithmetic for vector processors. Journal of Parallel and Distributed Computing 5(3), 250–270 (1988) 10. Nowak, F., Buchty, R., Kramer, D., Karl, W.: Exploiting the HTX-Board as a Coprocessor for Exact Arithmetics. In: Proceedings of the First International Workshop on HyperTransport Research and Applications (WHTRA 2009), February 2009, pp. 20–29. Computer Architecture Group, Institute for Computer Engineering (ZITI), University of Heidelberg (2009) 11. Buchty, R., Kramer, D., Kicherer, M., Karl, W.: A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous, Parallel, and Reconfigurable Architectures. In: Berekovic, M., Müller-Schloer, C., Hochberger, C., Wong, S. (eds.) ARCS 2009. LNCS, vol. 5455, pp. 60–71. Springer, Heidelberg (2009) 12. Fröning, H., Nüssle, M., Slogsnat, D., Litz, H., Brüning, U.: The HTX-Board: A Rapid Prototyping Station. In: Proceedings of the 3rd Annual FPGA World Conference (2006) 13. Kulisch, U.W.: Advanced Arithmetic for the Digital Computer: Design of Arithmetic Units. Springer, Secaucus (2002)
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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Organization IX Hartmut Schmeck Kar
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