Architecture of Computing Systems (Lecture Notes in Computer ...

200 R. Plyaskin and A. Herkersdorf
Fig. 1. Trace-based simulation
Thus, the workload generated by the component can be captured in the form of
asocalledtrace (Fig. 1).
A trace is a list of pseudocode constructs or trace primitives. Eachprimitive
defines an action which the abstracted module should perform. For example,
when executing a delay primitive (denoted as Delay in the figure) the abstracted
model of the CPU waits for a certain amount of time simulating a processing
latency. On execution of read or write primitives (denoted as Write and Read),
the CPU model issues correspondingly a read or write transaction to the memory
on the bus. The overall time required to access the memory module will depend
on the bus arbitration, data transfer latencies on the bus, and read/write latency
of the memory. Thus, the execution of the next delay primitive will be postponed
correspondingly. In [15], the authors demonstrate how trace-based simulations
can be applied for abstract application modeling and performance evaluation of
network processor architectures.
Since the internal functionality of the components is abstracted, performance
of trace simulations can be significantly increased compared to fully functional
and cycle accurate simulations, e.g. performed using an instruction set simulator
(ISS). In case of MPSoC architectures, the performance becomes a vital factor
since simultaneous instantiation of multiple cycle accurate CPU simulators can
significantly decrease the simulation time.
The trace representation allows system designers to describe a workload at
various levels of granularity. In a coarse-grained workload, traces contain approximated
processing latencies of a CPU without a detailed pattern of memory
accesses. This level of granularity may be of a great interest when the target SW
code is not available, but the designer can have an idea how the components
could interact with each other in the desired application [15].
In this paper, we propose to use abstract traces for accurate performance
estimation during high-level design space explorations of MPSoC architectures,
and address the challenge of how to derive accurate fine-grained traces. In our
approach, the traces are defined at the instruction level which allows achieving
exact bus access patterns and precise processing latencies of a CPU. We present
a complete workflow in which traces generated from a cycle accurate CPU simulator
are used for rapid evaluations of MPSoC architectures in our trace-based
SystemC TLM simulator. We demonstrate how the trace-based approach can be
applied during a design space exploration phase, when functional repartitioning