Architecture of Computing Systems (Lecture Notes in Computer ...

A Method for Accurate High-Level Performance
Evaluation of MPSoC Architectures Using
Fine-Grained Generated Traces
Roman Plyaskin and Andreas Herkersdorf
Institute for Integrated Systems, Technische Universität München,
Arcisstr. 21, 80290 Munich, Germany
{roman.plyaskin,herkersdorf}@tum.de
http://www.lis.ei.tum.de
Abstract. Performance evaluation at system level has become a prerequisite
in the design process of modern System-on-Chip (SoC) architectures.
This fact resulted in many simulative methods proposed by the
research community. In trace-based simulations, the performance of SoC
architectures is evaluated using abstracted traces. This paper presents an
approach for the generation of the traces at the instruction level from a
target SW code executed on a cycle accurate CPU simulator. We showed
that the use of fine-grained traces provides accuracy above 95% with
an increase of simulation performance by factor of 1.3 to 3.8 compared
to the reference cycle accurate simulator. The resulting traces are used
during high-level explorations in our trace-driven SystemC TLM simulator,
in which performance of MPSoC (Multiprocessor SoC) architectures
with a variable number of CPUs, diverse memory hierarchies and on-chip
interconnect can be evaluated.
1 Introduction
Constantly increasing complexity of System-on-Chip (SoC) architectures, stimulated
by the rising amount of transistors on a single chip, faces new challenges in
the design of integrated circuits. In order to shorten product development cycles
under high time-to-market pressure, early system-level modeling and simulation
has become a necessary part of the design process. Due to higher complexity
and many low-level details, cycle accurate system-level simulations are not feasible
from the perspective of simulation time. At system level, components are
typically modeled at a high level of abstraction allowing faster and more flexible
design space exploration. Therefore, the main challenge is to perform systemlevel
simulations fast and accurately at the same time.
For the performance evaluation, which is addressed in this paper, trace-based
simulations have been widely used for general purpose computer systems as
well as for systems-on-chip [7,8,10,11,13,15]. The trace-based approach represents
hardware components as black-box modules that either perform internal
processing or make read or write requests on the communication infrastructure.
C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 199–210, 2010.
c○ Springer-Verlag Berlin Heidelberg 2010