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148 Y. Liu et al. decreases, partial rollback occurs more frequently, and leading to the increasing of speedup. Fig. 5 shows the ratio of started transactions to committed transactions. A transaction needs to be restarted when rollback occurs due to a conflict; therefore this ratio reflects the frequency of rollbacks. The ratio value 1 indicates that there is no rollback occurs, and a bigger value means more rollbacks. As Fig. 5(a) shows, the ratio of flattening model increases rapidly with the increasing of processors, while the ratio of CPR scheme increases slowly, this is because that the conflict occurs more frequently when the processor number increases, and compared to rolling back to the outermost transaction, CPR rolls back partially whenever it is possible, therefore, the number of restarted transactions for partial rollback is far fewer than rolling back to the outermost transaction. Fig. 5(b) gives relationship between the ratio and nesting levels. It shows that the ratio of flattening model increases rapidly with the increasing of nesting levels, while the ratio of CPR keeps stable and stays at a low level. Two conclusions can be drawn from the above experiment results: firstly, CPR scheme outperforms flattening model in performance and scalability, in other words, with the increasing of processor number and nesting level, CPR scheme achieves better performance than flattening model; secondly, the performance of CPR scheme is correlative with the density of data sharing among nesting levels. 6 Conclusion Transactional memory can improve programmability of multi-core processors, avoid deadlock and furthermore, promote performance of concurrent programs. However, it also faces a series of challenges including transaction nesting. To support efficient closed nesting in hardware transactional memory, this paper proposes a CPR scheme which support conditional partial rollback on conflict without increasing hardware complexities significantly. Compared to the flattening model which is commonly-used in hardware transactional memory, the CPR scheme rolls back to the conflicted transaction itself or one of its outer-level transactions instead of the outermost if given conditions are satisfied. Transactional memory system architecture with support of the CPR scheme is also proposed based on multi-core processor and current cache coherent mechanisms. The system has been implemented by simulation. Its performance is evaluated by seven benchmark applications. Evaluation results show that the CPR scheme outperforms flattening model in performance and scalability. References 1. Herlihy, M., Eliot, J., Moss, B.: Transactional memory: Architectural support for lock-free data structures. In: 20th International Symposium on Computer Architecture, pp. 289–300. IEEE Computer Society, San Diego (1993)
Efficient Transaction Nesting in Hardware Transactional Memory 149 2. Hammond, L., Wong, V., Chen, M.: Transactional memory coherence and consistency. In: 31st International Symposium on Computer Architecture, pp. 102–113. IEEE Computer Society, Munich (2004) 3. Scott Ananian, C., Asanovic, K., Kuszmaul, B.C.: Unbounded transactional memory. IEEE Micro 26(1), 59–69 (2006) 4. Moore, K.E., Bobba, J., Moravan, M.J.: LogTM: log-based transactional memory. In: 12th International Symposium on High-Performance Computer Architecture, pp. 258–269. IEEE Computer Society, Austin (2006) 5. Bobba, J., Goyal, N., Hill, M.D.: TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In: 35th International Symposium on Computer Architecture (ISCA 2008), pp. 127–138. IEEE Computer Society, Beijing (2008) 6. Shavit, N., Touitou, D.: Software transactional memory. In: 14th annual ACM symposium on Principles of distributed computing, pp. 204–213. ACM Press, Ottawa (1995) 7. Saha, B., Adl-Tabatabai, A.-R., Hudson, R.L.: McRT-STM: a high performance software transactional memory system for a multi-core runtime. In: 11th ACM SIGPLAN symposium on Principles and practice of parallel programming, pp. 187–197. ACM, New York (2006) 8. Rajwar, Ravi, Goodman, James, R.: Transactional lock-free execution of lock-based programs. ACM Operating Systems Review 36(5), 5–17 (2002) 9. Adl-Tabatabai, A.-R., Lewis, B.T., Menon, V.: Compiler and runtime support for efficient software transactional memory. In: 2006 ACM SIGPLAN conference on Programming language design and implementation, pp. 26–37. ACM, Ottawa (2006) 10. Harris, T., Marlow, S., Jones, S.P.: Composable memory transactions. In: 2005 ACM SIGPLAN Symposium on Principles and Practise of Parallel Programming, pp. 48–60. ACM, Chicago (2005) 11. Rajwar, R., Herlihy, M., Lai, K.: Virtualizing transactional memory. In: 32nd International Symposium on Computer Architecture, pp. 494–505. IEEE Computer Society, Madison (2005) 12. Kumar, S., Chu, M., Hughes, C.J.: Hybrid transactional memory. In: 11th ACM SIGPLAN symposium on Principles and practice of parallel programming, pp. 209–220. ACM, New York (2006) 13. McDonald, A., Carlstrom, B., Chung, J.W.: Transactional memory: The hardwaresoftware interface. IEEE Micro 27(1), 67–76 (2007) 14. Baugh, L., Neelakantam, N., Zilles, C.: Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory. In: 35th International Symposium on Computer Architecture (ISCA 2008), pp. 115– 126. IEEE Computer Society, Beijing (2008) 15. Harris, T., Cristal, A., Unsal, O.: Transactional memory: An overview. IEEE Micro 27(3), 8–20 (2007) 16. Moravan, M.J., Bobba, J., Moore, K.E.: Supporting Nested Transactional Memory in LogTM. In: 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (October 2006) 17. Magnusson, P.S.: Simics: A Full System Simulation Platform. IEEE Computer (February 2002) 18. Martin, M.M.K., Sorin, D.J., Beckmann, B.M.: Multifacet’s General Executiondriven Multiprocessor Simulator (GEMS) Toolset. Computer Architecture News, CAN (September 2005)
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Abdullah, Tariq 174 Alima, Luc Onan
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