Architecture of Computing Systems (Lecture Notes in Computer ...

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22 G. Aşılıoğlu, E.M. Kaya, and O. Ergin The head pointers of each FIFO queues are also separate registers that are updated from the commit stage of the pipeline. When an instruction is committed and removed from the reorder buffer it simply increments the head pointer of its destination architectural register. Note that instructions do not access the payload area from the commit stage but they only access the head pointer register. Processor is stalled at the rename stage if the contents of the head pointer register is just one over the contents of the tail pointer register for an architectural register that needs to be renamed. Since these registers are just incremented unless there is an exception (such as a branch misprediction), they are better be implemented as a counter with parallel data loading capability. The checkpoint table that is needed to recover the contents of the pointer register in case of an exception or misprediction is a plain payload structure that only holds the values of the registers just at the time a branch reaches the rename stage. That structure is implemented by using SRAM bitcells and it is smaller than a register file which makes it possible to access this structure in less than a cycle. Complexity is moved to the pointer registers in the proposed scheme since these registers are actually counters but they also need a logic for immediate data loading and comparison of head and tail pointers. There is also a control logic that allows the reading and writing of values by using only the contents of the tail pointer. 7 Results and Discussions In order to get an accurate idea of the performance impact of the proposed technique we used the PTLsim simulator [8] that is capable of simulating x86 instructions. We ran the spec 2000 benchmarks for 1 billion committed instructions. Table 1 shows the simulated processor configuration. The simulation was run with checkpointing and walk-backwards recovery mechanisms already included in PTLsim. The FIFO tests were based on a modification of the checkpointing algorithm which imposed penalties to the cycle count of the simulation when the allocated queue was filled, and performed similar to checkpointing when the queues had available space. Table 1. Simulation Parameters Parameter Configuration Machine width 4-wide fetch, 4-wide issue, 4-wide commit Window size 32 entry issue queue, 48 entry load queue, 32 entry store queue, 128– entry ROB Function Units Integer ALU (2), Load unit (2), FPU (2), Store Unit (2) Latencies Integer ALU (1), ALU Multiplication (4), ALU Bit scans(3), ALU Division (32), FPU Arithmetic (6), FPU Vector Arithmetic (1) L1 I-Cache 32 KB, 4-way set-associative, 64 byte line, 1 cycle hit time L1 D-Cache 16 KB, 4–way set–associative, 64 byte line, 1 cycle hit time L2 Unified Cache 256 KB , 16–way set–associative, 64 byte line, 6 cycles hit time L3 Unified Cache 4 MB, 32–way set–associative, 64 byte line, 16 cycles hit time Branch Predictor Meta predictor using bimodal and two-way Memory 140 cycles hit time
Complexity-Effective Rename Table Design for Rapid Speculation Recovery 23 Fig. 5. Performance comparsion of the proposed scheme against regular checkpointing and walk-backwards scheme Fig. 5 shows the performance comparison of the proposed renaming scheme when compared against regular checkpointing. The results for the walk-back scheme is also shown on the graph. The y-axis of the graph is the percent decrease of IPC. Zero on the y-axis means that the method has the same IPC as checkpointing. For the proposed scheme there are two graphs: one labeled as fifo ipc and one labeled as fifo ipc adjusted. For the first bar, we used a constant FIFO size of 16 for each architectural register, whereas for the adjusted bar we adjusted the size of the FIFO queues of each architectural register according to the average and maximum values shown in Fig. 3. In the latter case, the sizes of the FIFO queue were set to numbers between 16 and 32. We assumed a recovery time of 2 cycles for the proposed scheme although it may be possible to recover in one cycle depending on the circuit level implementation. Results in Fig. 5 show that checkpointing always outperforms walking through the reorder buffer and the proposed scheme almost meets the performance of checkpointing although it limits the number of instances of the architectural registers that can be present inside the processor. Interestingly increasing the sizes of the FIFO queues did not provide any significant performance benefits. 8 Conclusion and Future Work In this paper we proposed a FIFO-queue-based rename table design that is scalable and allows faster and simple branch misprediction recovery. Each architectural register is assigned a FIFO queue that holds every speculative physical register assignment. By using another checkpoint table that holds the tail pointers for each queue, it is possible to recover the rename table in a single cycle by just using the regular SRAM bitcells rather than shift registers. Our design simplifies the circuits used for constructing the rename table especially for processors that employ checkpointing. If implementing the regular checkpointing scheme is feasible in terms of circuit complexity, proposed scheme is not a good alternative; using the regular checkpointing is a better choice. However, the proposed renaming scheme offers the power of
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Abdullah, Tariq 174 Alima, Luc Onan
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