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10 J. Mische et al. % of unused pipeline cycles 100 80 60 40 20 0 branch memfix membusy pipeline fetch 0/0 1/0 2/0 0/1 1/1 2/1 0/2 1/2 2/2 0/3 1/3 2/3 0/1+1/1+2/1+0/2+1/2+2/2+0/3+1/3+2/3+ instruction / data memory access latency Fig. 3. Reason why the HPT cannot be issued, depending on the memory latencies When executing multiple threads, the HPT reaches exactly 100% of its singlethreaded speed, hence a WCET analysis for a singlethreaded simplification of our architecture is also valid for the HPT in the multithreaded architecture [3]. The speed of the threads with lower priorities falls exponentially to about 50, 35 and 20 percent of singlethreaded performance (measured in Instructions Per Cycle, IPC), see [3] for a more detailed discussion. We used the Hightec GNU C/C++ compiler for TriCore [18] to compile benchmark programs from the EEMBC AutoBech 1.1 benchmark suite [20] (a2time, canrdr, aifirf, rspeed)andtheMälardalen WCET group [21] (crc, fft1, mm). 1000 task-sets of 8 threads were randomly assembled from these seven benchmark and executed for one million cycles each. The given figures are the average values of these 1000 runs. 5.1 Reasons for Stalling Threads The reasons why a thread cannot issue any instructions in a certain cycle can be divided into five classes: branch. Fixed latency of a branch: 2 cycles memfix. Minimum latency of a memory access: 3 cycles membusy. Additional stall cycles, when a memory instruction cannot be executed, because the memory is busy with an operation from another thread. pipeline. The desired pipeline is already occupied by a higher priority thread. (never applies to the HPT) fetch. The instruction window is empty. Fig. 3 shows the distribution of the reasons for not issuing instructions of the highest priority thread (HPT), depending on the memory latencies. The x-axis gives the reason for a delay and the numbers on the x-axis indicate the memory latencies: the first number is the latency of the instruction memory, the second one the latency for data memory.
% of unused pipeline cycles 100 80 60 40 20 0 branch membusy memfix pipeline data latency 0 How to Enhance a Superscalar Processor 11 fetch data latency 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 priority data latency 2 Fig. 4. Reason why a thread cannot issue an instruction, depending on its priority Even with minimum latencies (0/0), more than 80% of unused cycles are due to memory delays (fetch or memfix). Not surprisingly the percentage is increased when the latencies are increased. Each additional cycle of instruction memory latency increases the percentage of fetch stalls by 8%, therefore a fast instruction connection (via scratchpad or instruction cache) is inevitable. The bars marked with plus show additional membusy latencies. These appear, when the HPT is executed together with other threads (for the bars without a plus, the HPT was executed without concurrent threads). If a lower priority memory access takes multiple cycles and begins in the cycle preceding the cycle when a HPT memory access should start, the former occupies the memory controller for multiple cycles and therefore delays the HPT thread. This effect violates the complete isolation (and thus the hard real-time capability of the HPT), but it can be avoided by either modifying the WCET analysis and assuming twice the memory latency or the lower priority memory accesses can be delayed when a HPT memory access is on the way through the pipeline (then the distribution of reasons is the same as in the corresponding case without the plus). ThelatertechniqueiscalledDominant Memory Access Announcing (DMAA): when a memory access of the HPT is recognized at the beginning of the pipeline, it is announced immediately to the memory controller that consequently delays all memory accesses until the HPT memory access arrives and can be invoked. Therefore all memory accesses between issue stage and memory controller are delayed and if the distance between them is longer than the memory latency, the HPT is never influenced by lower priority memory accesses (for details see [3]). Applying the DMAA technique, Fig. 4 shows the average distribution of stall reasons against the priority. The fixed latencies (which dominate the stall reasons of the HPT) are less important for lower priority threads. For these threads, the influence of fetch and pipeline conflicts grows significantly. If the memory latency is more than zero (rightmost group of Fig. 4), this stall reason dominates for lower priority threads.
Page 2 and 3: Lecture Notes in Computer Science 5
Page 4 and 5: Volume Editors Christian Müller-Sc
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Page 8 and 9: Organization IX Hartmut Schmeck Kar
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130 M. Kayaalp et al. INSTRUCTION 1
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Abdullah, Tariq 174 Alima, Luc Onan
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