Architecture of Computing Systems (Lecture Notes in Computer ...

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A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics Fabian Nowak and Rainer Buchty Chair for Computer Architecture Karlsruhe Institute of Technology 76128 Karlsruhe, Germany {nowak,buchty}@kit.edu Abstract. Processor speed and available computing power constantly increases, enabling computation of more and more complex problems such as numerical simulations of physical processes. In this domain, however, the problem of accuracy arises due to rounding of intermediate results. One solution is to avoid intermediate rounding by using exact arithmetic. The use of FPGAs as application-specific accelerators can speed up such operations compared to their software implementation. In this paper, we present a system approach employing state-of-the art FPGA and interconnection technology for exact arithmetic with doubleprecision operands, delivering up to 400M exact MACs/s in total and providing a speedup of up to 88 times over competing software implementations in the case of matrix multiplication. 1 Introduction With the computation of increasingly complex problems, accuracy issues arose related to rounding effects taking place in current FPU implementations. These may lead to unsatisfying results and even physical damage, if upfront simulations do not indicate certain problems. This problem is typically addressed by certain exact arithmetics built into mathematics and simulation packages. Such arithmetics increase the width of the internal data representation or concatenate several floating-point numbers in order to enlarge the “accuracy window” in which no rounding is necessary. While these software implementations provide a viable workaround, they are magnitudes slower than native hardware support. Custom accelerator hardware can speed up such operations using several design techniques, e.g. pipelined execution and parallelization. We therefore present an accelerator system for exact arithmetics. Based on a careful examination of the underlying algorithm for implementing exact arithmetics, a hardware solution employing pipelining techniques and exploiting parallelism is proposed delivering up to 400M exact MAC operations per second. In the remainder, we first outline related work in Section 2. We then present our general architecture design in Section 3 before discussing implementation issues and viable solutions in Section 4. The elaborated design is thoroughly evaluated in Section 5. We conclude this paper by summing up the results and presenting our plans for future work in Section 6. C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 222–233, 2010. c○ Springer-Verlag Berlin Heidelberg 2010
A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics 223 2 Related Work Performing floating-point operations in software is quite costly, therefore many FP accelerators exist. Such accelerators were originally the domain of dedicated silicon, but with increasing FPGA capabilities, these gained attention as computation accelerators. In [1], for example, double-precision operations are employed for accelerating physics simulations. Other work focuses on exploiting FPGAs for matrix multiplications with double precision [2], or on the conjugate gradient method [3,4,5]. The problem of exact computation is well-understood, and hence multiple solutions exist. For certain computations, the effect of errors can be evaluated upfront, allowing the use of lower-precision computation [6]. For computations where knowledge of the included error is required, using so-called Staggered Interval Arithmetics [7] (SIA) is an option. The precision of floating-point operations can also be enhanced by increasing mantissa and exponents as e.g. provided by the GNU MP library. Our work is motivated by the work of Kulisch et al. [8],[9], who developed a concept for exact arithmetics support in regular floating-point units and also implemented a PCI-attached coprocessor for exact arithmetics. Following Kulisch’s work, a straight-forward implementation supporting single-precision operands demonstrated the general applicability to FPGA technology, but did not yet offer speedup in comparison to software implementations [10]. In order to further support the use of such accelerators and to ease benchmarking, we developed a runtime system enabling dynamic switching from conventional to exact arithmetics implemented in software or hardware [11]. Dynamically applying exact arithmetics only where required, results in the fastest total runtime while still guaranteeing numerical robustness and therefore delivering precise results. 3 Architecture and Design The need for exact arithmetics in numerical programs arises in most cases for matrix multiplications. Thus, we give a detailed description of how matrix multiplication can be split and organized in the optimal way for data transfers and parallel pipelined processing in this section. 3.1 Exploiting Matrix Multiplication Properties Matrix multiplications can be regarded as consisting of matrix-vector multiplications that are simply a series of inner vector products: ⎛ ⎞ ⎛ ⎞ C = A · B = ⎜ ⎝ a1 . am ⎟ ⎠ · � � � � b1 ··· bo = A · b1 ··· A · bo = ⎜ ⎝ a1 • b1 ··· a1 • bo . . .. . am • b1 ··· am • bo ⎟ ⎠ (1)
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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