Architecture of Computing Systems (Lecture Notes in Computer ...

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240 F. Xudong et al. threads in the wavefront have to execute the branch, which means all the paths are executed serially. This situation degrades the kernel performance greatly. Therefore branch divergences in kernels should be eliminated as much as possible. We convert control dependence to data dependence, which caters to GPUs powerful data processing capability [10]. Our branch elimination is a two-step strategy: a) Branch fusion. Our branch fusion here is only suitable for the situation where the left expressions of if and else are the same. If not, there is no benefit using branch fusion since the expressions in both branches have to be executed. b) Expression simplification. The second step is used to simplify expressions gotten from branch fusion in the hope of eliminating all the redundant computations. With branch elimination, we can eliminate all the eight branches in the Interp kernel. 3.4 CPU-GPU Task Distribution GPUs are good at performing ALU-intensive tasks, which qualifies them as good accelerators for CPUs. The philosophy of using GPUs to accelerate applications is to manipulate massive threads to exploit parallelism among threads and hide memory access latencies. So when the problem size is very small, there may be not enough threads to occupy stream processing cores to fully exploit parallelism. Take the problem size 16 3 for example. Assuming that there are enough GPRs, only 4K threads are needed to process the computation under this problem size, which is much less than the maximum 10K threads that the RV770 core can provide, not to mention the smaller problem sizes. When the speedup obtained by the GPU is less than one, we should consider turning the task back to run on the CPU. Nevertheless, porting computing tasks to the CPU entails inevitable overhead such as data communication latency. This indicates the performance gain from distributing the task among the CPU and the GPU must counteract this overhead for the purpose of improving the overall system performance. Distributing tasks between the CPU and the GPU is sure to outperform the CPU- or GPU-single computing device execution. 4 Experimental Evaluation To examine the benefits of our optimization strategies, we implemented the Mgrid application using Brook+ on an AMD Radeon HD4870 GPU. All the results are compared to the single-thread CPU version, which is measured on an Intel Xeon E5405 CPU running at 2GHz with 256KB L1 cache and 12MB L2 cache. We used the Intel ifort compiler as the CPU compiler with the optimization option -O3. Mgrid is a 3D multigrid application in the SPECfp/NAS benchmark. Notably, it is the only application found in both the SPEC and NAS benchmark suites, and among those few SPEC 2000 applications surviving through SPEC 95 and SPEC 98. The main process of Mgird is of a V-cycle pattern performed at multilevel grids in multi-pass (multiple iterations), as illustrated in Fig. 1(b). Mgrid
Optimizing Stencil Application on Multi-thread GPU Architecture 241 spends 85% of its execution time performing stencil computations on 3D arrays, which go through all of the four primary kernels, including Resid, Psinv, Rprj3, and Interp. TheResid kernel computes the residual. The Psinv kernel computes the approximate inverse. The Rprj3 kernel computes the projection from fine grid to coarse grid. The Interp kernel computes the interpolation from coarse grid to fine grid. 4.1 Effects of Improving Thread Utilization Here we examine the effectiveness of improving thread utilization. Applying the strategies proposed in Subsection 3.1, we used four thread granularities: double, double2, double2 plus two output streams, and double2 plus four output streams. If a thread using double can compute N points, then a thread using double2, double2 plus two output streams and double2 plus four output streams can compute 2N, 4N, and 8N points, respectively. For conveniences sake, we used N, 2N, 4N and 8N to denote different thread granularities. Fig. 2(a) shows the speedup of the Resid kernel over the CPU implementation under different problem sizes using the four thread granularities. Note that since our optimization strategies target stencil computations in Mgrid, whenevaluating a single kernel, we do not count in the time consumed by loading the kernels to the GPU and by the periodical communication subroutine Comm3 in each kernel. Nevertheless, in our overall evaluation for Mgrid, all the time will be counted. As shown in Fig. 2(a), the thread granularity 8N demonstrates the best performance under problem size 256 3 and 128 3 , while 4N yields the best performance under the other two problem sizes. Problem sizes smaller than 32 3 are not shown in the figure since their speedups are less than one. We can see that under large problem sizes 256 3 and 128 3 , the speedup for each kernel scales up with the granularity. This is because under large problem size, large thread granularity provides more chances to exploit intermediate result reuse within threads, yet there are enough threads to exploit parallelism among threads. However, under small problem size, large thread granularity requires more GPRs in each thread, thus impacting the number of threads and resulting in limited parallelism among threads. Under problem size 64 3 and 32 3 , the speedups first scale with the granularity, reach a maximum in granularity 4N, and then decrease in granularity 8N, see Fig. 2(a). The performance gain through hitting more data reuse within each thread using large granularity (8N) is offset by the performance loss caused by lacking enough threads to fully occupy parallel stream computing cores. Fig. 2(b) shows the speedup of each kernel and the whole application Mgrid under the largest problem size 256 3 . We can see that the speedups of the kernel Resid and Psinv scale up with the thread granularity monotonously. This is because large thread granularity is favorable for intermediate data reuse within each thread, while there are abundant threads for thread level parallelism. Interp computes the coarse grid through accessing the finer grid, so it tends to be an ALU-intensive kernel. The speedup of the Interp kernel increases rapidly with the thread granularity and reaches a maximum in thread granularity 4N, see
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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How to Enhance a Superscalar Proces
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4 J. Mische et al. The Real-time Vi
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Exploiting Inactive Rename Slots fo
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130 M. Kayaalp et al. INSTRUCTION 1
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148 Y. Liu et al. decreases, partia
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