Architecture of Computing Systems (Lecture Notes in Computer ...

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130 M. Kayaalp et al. INSTRUCTION 1 D: R1 S1: R2 S2: R3 C1 C2 C3 = = = C6 INSTRUCTION 2 C4 C5 = D: R2 S1: R1 S2: R1 = = INSTRUCTION 3 Fig. 2. Error detection example for single instruction renaming instructions are stored [14], is employed. The instruction slots that hold the redundant information are marked as “bogus” in order to let the rename logic know that these tags do not belong to real instructions. After the single instruction’s tags are replicated in the empty slots, outputs of the already wired comparators at the rename stage are checked to see if an error occurred by the time instruction arrived at the rename stage. As seen in Fig. 2, if the outputs of the comparators C2 and C3 mismatch it can only be the result of an error on the destination register identifier of the instruction. Similarly, the outputs of the comparators C8 and C9 are checked in order to detect an error on the first source tag of the instruction. As for the destination tag, in fact even a mismatch signal in C2 or C3 indicates that an error has occurred. Using the output of the both comparators actually gives a chance to correct the error if one assumes a single event upset model. In order to cover both source tags and the destination tag of the single instruction the processor needs to be capable of renaming at least 4 instructions each cycle. Although the Fig. 2 is shown for a 3-wide machine for simplicity, the second source tag of the first instruction is copied to the destination field of the third instruction as it would be done in a 4-wide machine. 3.1.1 Single Event Upset Model If we assume that the fault-rate is sufficiently low, then we can statistically ignore the probability of a multiple-bit flip. This is typically called the Single Event Upset model. Under this assumption, the bit flip can not only be detected but corrected as well. Consider Fig. 2, and assume that there was a bit flip affecting R1. There are two possible cases: a) The bit flip could occur in the destination field of instruction 1; then both C2 and C3 comparators would signal a mismatch, indicating that there was a strike to the destination field of instruction 1. The field is updated by copying the field of either S1 or S2 of instruction 2, which hold the copies of R1. C7 C8 C9 = = = D: R3 S1: R2 S2: R2
Exploiting Inactive Rename Slots for Detecting Soft Errors 131 b) The bit flip could occur on the copies of R1 held in the S1 or the S2 fields of instruction 2. In this case a mismatch in either C2 or C3 would indicate a flip in S1 or S2 respectively. The error could then be corrected by updating the faulty field or would not be corrected at all since the actual tag value is free of errors. 3.1.2 Multiple Events Upset Model If the fault-rate is high, then multiple bit-flips could occur. The fault-recovery for this model is slightly more complicated; however even for this case we can detect the fault. In this model, it is not for sure that the “correction” will lead to the actual value of the tag. For example if C2 indicates a mismatch and or C3 indicates a match it is logical to think that an error occurred on the first source field of instruction 2. However it is also possible that both the real tag and the copy residing in the second source field may be erroneous. Assuming that the actual tag is free of errors in this case may be wrong although the probability of actual tag being correct is high. Therefore it makes sense to flush the pipeline and refetch the instruction if any of the comparators give a mismatch signal. It is possible to correct errors that occur on the tags of the single instruction. However this comes at the cost of sacrificing the protection on one of the tags since there are not enough comparators to check three tags in a 4-wide machine. In order to correct an error on R1 for the example shown in Fig. 2, the tag R1 has to be copied to the destination field of the instruction 2. This way there will be 3 comparisons for R1 and simple voting can be employed. Note that different from regular voting used to correct or detect errors, more copies of the same value are held here since we can only compare a destination tag to a source or destination tag of another instruction but we cannot compare two source tags with each other using only the already available hardware resources. Although not shown in Fig. 2, source register R3 is also copied to the source fields of the instruction slot 4 for protection in a processor with a 4-wide rename stage. When the destination tag is replicated to all of the fields of the second instruction, an error in the actual tag will result in a mismatch signal at C1, C2 and C3 at the same time. By copying one of the replicated values back into the actual tag area corrects the problem. However if there is even 1 match signal, it probably means that the replicas are corrupted since having two errors, one on the actual value and one on a replica, that will result to the same faulty value is a low probability. Yet again, it may be a good choice to flush the pipeline and refetch the instruction in such a case. 3.2 Protecting the Tags of Two Instructions Renamed in the Same Cycle The processor renames one instruction at a cycle only if there is a problem. This problem may be a cache miss, a taken branch or a processor resource that causes a bottleneck temporarily. When the processor starts to execute the program faster, the number of instructions renamed per cycle increases. However as the throughput of the processor increases, the benefits of our technique decrease as more comparators start to be employed for their real purpose. For a 4-wide processor, when only two instructions are renamed together, it is possible to correct an error that occurs on both of the destination tags of the instructions but we cannot detect or correct any errors occurring on the source tags at the same
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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How to Enhance a Superscalar Proces
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4 J. Mische et al. The Real-time Vi
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6 J. Mische et al. 4.1 Instruction
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8 J. Mische et al. Additionally the
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10 J. Mische et al. % of unused pip
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12 J. Mische et al. % of cycles spe
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14 J. Mische et al. 16. Lickly, B.,
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16 G. Aşılıoğlu, E.M. Kaya, and
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26 T.B. Preußer, P. Reichel, and R
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38 P. Bellasi, W. Fornaciari, and D
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50 J. Zeppenfeld and A. Herkersdorf
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62 B. Jakimovski, B. Meyer, and E.
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74 M. Bonn and H. Schmeck Fig. 1. J
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76 M. Bonn and H. Schmeck 2.2 Node
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78 M. Bonn and H. Schmeck Uptime-ba
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180 T. Abdullah et al. Messages 140
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182 T. Abdullah et al. (except when
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184 T. Abdullah et al. % Matchmakin
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186 T. Abdullah et al. show that th
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200 R. Plyaskin and A. Herkersdorf
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224 F. Nowak and R. Buchty where A
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226 F. Nowak and R. Buchty Fig. 3.
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228 F. Nowak and R. Buchty Table 2.
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230 F. Nowak and R. Buchty Table 4.
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232 F. Nowak and R. Buchty 5.3 Comp
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Optimizing Stencil Application on M
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238 F. Xudong et al. stencil comput
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240 F. Xudong et al. threads in the
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242 F. Xudong et al. Speedup 14 12
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244 F. Xudong et al. 5 Related Work
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Abdullah, Tariq 174 Alima, Luc Onan
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