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244 F. Xudong et al. 5 Related Work With the popular adoption of GPUs in scientific computing, much research has recently been performed in optimizing GPU applications using general programming languages such as Brook+ and CUDA. Ryoo et al. proposed optimization principles for efficient mapping of computation to graphics hardware [11]. Their main concern was using massive multithreading to exploit the rich stream core resource and hide memory fetch latency. Jang et al. presented an optimization methodology that utilizes architectural information to accelerate programs on AMD GPUs [12]. They exploited optimizations by defining optimization spaces. Their work demonstrated many AMD GPU details. Wang et al. presented GPU implementation of Mgrid using CUDA in the single precision floating point version [13]. They exploited data locality in 3-level memory hierarchies and tuned thread granularity thus reducing the pressure on the off-chip memory bandwidth. Due to architecture deviation, their optimization strategies can not directly applied using Brook+ on AMD GPUs. In our work, we choose Mgrid since its stencil computations provide rich opportunity for exploiting on-chip parallelism and hiding memory accessing latencies. Li et al. proposed a compiler framework for automatic tiling of iterative stencil loops to improve the cache reuse [14]. Krishnamoorthy et al. developed an approach for automatic parallelization of stencil codes, explicitly addressing the issue of load-balanced execution of tiles caused by loop skewing in the time dimension [4]. They focused on improving cache locality of the CPU. 6 Conclusions and Future Work In this paper, we implemented and optimized a real benchmark application Mgrid on AMD Radeon HD4870 GPU, and achieved very good experimental results. Though our implementation and optimizations are based on Mgrid, theoptimization strategies can be use to improve any stencil computations. In the future, we would like to determine thread granularity automatically to simplify the application optimization on the GPU; and we would also consider exploring the GPU application performance at the intermediate language (IL) level. To fully exploit the CPU and GPU heterogeneous platform, we would try to automatically distribute tasks between the two computing resources. References 1. AMD.: Ati stream computing user guide v1.4beta (2009), http://developer.amd.com/gpu_assets/Stream_Computing_User_Guide.pdf 2. NVIDIA.: Compute unified device architecture programming guide v2.1beta (2009), http://developer.download.nvidia.com/compute/cuda/ 1 0/NVIDIA CUDA Programming Guide 1.0.pdf
Optimizing Stencil Application on Multi-thread GPU Architecture 245 3. Ryoo, S., Rodrigues, C.I., Baghsorkhi, S.S., Stone, S.S., Kirk, D.B., Hwu, W.m.W.: Optimization principles and application performance evaluation of a multithreaded gpu using cuda. In: PPoPP 2008: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, pp. 73–82. ACM, New York (2008) 4. Krishnamoorthy, S., Baskaran, M., Bondhugula, U., Ramanujam, J., Rountev, A., Sadayappan, P.: Effective automatic parallelization of stencil computations. SIG- PLAN Not. 42(6), 235–244 (2007) 5. Fan, Z., Qiu, F., Kaufman, A., Yoakum-Stover, S.: Gpu cluster for high performance computing. In: SC 2004: Proceedings of the 2004 ACM/IEEE conference on Supercomputing, Washington, DC, USA, p. 47. IEEE Computer Society Press, Los Alamitos (2004) 6. Buck, I.: Brook specification v0.2 (2003), http://hci.stanford.edu/cstr/reports/2003-04.pdf 7. Ryoo, S., Rodrigues, C.I., Stone, S.S., Stratton, J.A., Ueng, S.-Z., Baghsorkhi, S.S., Hwu, W.-m.W.: Program optimization carving for gpu computing. J. Parallel Distrib. Comput. 68(10), 1389–1401 (2008) 8. Mohan, T., de Supinski, B.R., McKee, S.A., Mueller, F., Yoo, A., Schulz, M.: Identifying and exploiting spatial regularity in data memory references. In: SC 2003: Proceedings of the 2003 ACM/IEEE conference on Supercomputing, Washington, DC, USA, p. 49. IEEE Computer Society, Los Alamitos (2003) 9. Harris, M.J., Baxter, W.V., Scheuermann, T., Lastra, A.: Simulation of cloud dynamics on graphics hardware. In: HWWS 2003: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, Aire-la-Ville, Switzerland, Switzerland, pp. 92–101. Eurographics Association (2003) 10. Allen, J.R., Kennedy, K., Porterfield, C., Warren, J.: Conversion of control dependence to data dependence. In: POPL 1983: Proceedings of the 10th ACM SIGACT- SIGPLAN symposium on Principles of programming languages, pp. 177–189. ACM, New York (1983) 11. Ryoo, S., Rodrigues, C.I., Baghsorkhi, S.S., Stone, S.S., Kirk, D.B., Hwu, W.-m.W.: Optimization principles and application performance evaluation of a multithreaded gpu using cuda. In: PPoPP 2008: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, pp. 73–82. ACM, New York (2008) 12. Jang, B., Do, S., Pien, H., Kaeli, D.: Architecture-aware optimization targeting multithreaded stream computing. In: GPGPU-2: Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, pp. 62–70. ACM, New York (2009) 13. Wang, G., Yang, X.J., Zhang, Y., Tang, T., Fang, X.D.: Program optimization of stencil based application on the gpu-accelerated system. In: Intl. Symposium on Parallel and Distributed Processing and Applications, pp. 219–225 (2009) 14. Li, Z., Song, Y.: Automatic tiling of iterative stencil loops. ACM Trans. Program. Lang. Syst. 26(6), 975–1028 (2004)
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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