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36 T.B. Preußer, P. Reichel, and R.G. Spallek References 1. Zabel, M., Preußer, T.B., Reichel, P., Spallek, R.G.: Secure, real-time and multithreaded general-purpose embedded Java microarchitecture. In: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp. 59–62. IEEE, Los Alamitos (2007) 2. Holloway, J., Steele Jr., G.L., Sussman, G.J., Bell, A.: The SCHEME-79 chip. Technical report, Massachusetts Institute of Technology, Artificial Intelligence Lab. (1980) 3. Moon, D.A.: Garbage collection in a large LISP system. In: LFP 1984: 1984 ACM Symposium on LISP and functional programming, pp. 235–246. ACM, New York (1984) 4. Nilsen, K.D., Schmidt, W.J.: Hardware support for garbage collection of linked objects and arrays in real-time. In: ECOOP/OOPSLA 1990 Workshop on Garbage Collection (1990) 5. Nilsen, K.D., Schmidt, W.J.: Cost-effective object space management for hardwareassisted real-time garbage collection. ACM Lett. Program. Lang. Syst. 1(4), 338– 354 (1992) 6. Meyer, M.: A true hardware read barrier. In: ISMM 2006: 5th International Symposium on Memory Management, pp. 3–16. ACM, New York (2006) 7. Srisa-an, W., Dan Lo, C.-T., Chang, J.-e.M.: Active memory processor: A hardware garbage collector for real-time Java embedded devices. IEEE Transactions on Mobile Computing 2(2), 89–101 (2003) 8. Pfeffer, M., Ungerer, T., Fuhrmann, S., Kreuzinger, J., Brinkschulte, U.: Real-time garbage collection for a multithreaded Java microcontroller. Real-Time Syst. 26(1), 89–106 (2004) 9. Uhrig, S., Wiese, J.: Jamuth: an IP processor core for embedded Java real-time systems. In: Bollella, G. (ed.) JTRES 2007. ACM International Conference Proceeding Series, pp. 230–237. ACM, New York (2007) 10. Meyer, M.: A novel processor architecture with exact tag-free pointers. IEEE Micro 24(3), 46–55 (2004) 11. Meyer, M.: An on-chip garbage collection coprocessor for embedded real-time systems. In: RTCSA 2005: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Washington, DC, USA, pp. 517– 524. IEEE Computer Society, Los Alamitos (2005) 12. Gruian, F., Salcic, Z.A.: Designing a concurrent hardware garbage collector for small embedded systems. In: Asia-Pacific Computer Systems Architecture Conference, pp. 281–294 (2005) 13. Schoeberl,M.:JOP:AJavaoptimizedprocessor.In:Meersman,R.,Tari,Z.(eds.) OTM-WS 2003. LNCS, vol. 2889, pp. 346–359. Springer, Heidelberg (2003) 14. Reichel, P.: Entwurf und Implementierung verschiedener Garbage-Collector- Strategien für die Java-Plattform SHAP. Großer beleg, Technische Universität Dresden (2007) 15. Anton, A.: OpenFIRE (2007), http://www.opencores.org/project,openfire2 16. Harboe, Ø.: ZPU - the worlds smallest 32 bit CPU with GCC toolchain (2008), http://www.opencores.org/project,zpu 17. Henry, G., Baker, J.: List processing in real time on a serial computer. Commun. ACM 21(4), 280–294 (1978) 18. Gagnon, E.M., Hendren, L.J.: SableVM: A research framework for the efficient execution of Java bytecode. In: Java Virtual Machine Research and Technology Symposium, April 2001, pp. 27–40 (2001)
A Hierarchical Distributed Control for Power and Performances Optimization of Embedded Systems Patrick Bellasi 1 , William Fornaciari 1 ,andDavidSiorpaes 2 1 Politecnico di Milano, P.zza Leonardo da Vinci, 32. 20133 - Milano, Italy bellasi@elet.polimi.it, fornacia@elet.polimi.it 2 STMicroelectronics, Via C. Olivetti, 2. 20041 - Agrate Brianza, Italy david.siorpaes@st.com Abstract. Power and resource management are key goals for the success of modern battery-supplied multimedia devices. This kind of devices are usually based on SoCs with a wide range of subsystems, that compete in the usage of shared resources, and offer several power saving capabilities, but need an adequate software support to exploit such capabilities. In this paper we present Constrained Power Management (CPM), a cross-layer formal model and framework for power and resource management, targeted to MPSoC-based devices. CPM allows coordination and communication, among applications and device drivers, to reduce energy consumption without compromising QoS. A dynamic and multiobjective optimization strategy is supported, which has been designed to have a negligible overhead on the development process and at run-time. 1 Introduction New generation of mobile devices are usually based on platforms using a Multi- Processor System-on-Chip (MPSoC) which is composed of many subsystems and surrounded by a broad set of peripherals. Each subsystem is typically characterized by several working modes (WMs), with corresponding different levels of Quality-of-Service (QoS) provided and power consumptions profiles. Modern hardware technologies increased the capability to reduce both dynamic and static power consumptions [1]. However, several mechanisms to save power at circuit level require an adequate software support to be effectively exploited. Indeed, to properly satisfy applications’ QoS demands it is required to track system resources availability and usage which directly impact on energy consumptions. Moreover the need for support of heterogeneous usage scenarios makes the management of resources and power saving a challenging design goal. This work introduce the general idea behind the definition of a system-wide power and performances optimization strategy, to be implemented at OS level. This solution has been designed to be sufficiently portable among different platforms, without compromising too much its accuracy and efficiency, and easily adapt to all possible different device usage scenarios. We prove that a hierarchical C. Müller-Schloer, W. Karl, and S. Yehia (Eds.): ARCS 2010, LNCS 5974, pp. 37–48, 2010. c○ Springer-Verlag Berlin Heidelberg 2010
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Abdullah, Tariq 174 Alima, Luc Onan
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