IntelÃ‚Â® Server System Server System "Emerald Ridge ... - CTL

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Intel® Server System "Emerald Ridge” Integrated Baseboard Management Controller EPSIPMI Command Interface10. IPMI Command InterfaceThis chapter defines the requests (commands) that the BMC accepts, and the correspondingfunctionality and request / response data for these commands. These commands direct theBMC to perform actions. The commands are sent to the BMC from the IPMB, LPC, or LANinterfaces. For information on which interface supports which commands, see Table 67 throughTable 72.For the base specification and descriptions of BMC commands other than those specified in thischapter, see the Intelligent Platform Management Interface Specification.The BMC implements the event receiver, SEL, SDR, FRU, and sensor devices, as described inthe Intelligent Platform Management Interface Specification.10.1 Command QueuingThe BMC implements two command handlers:An interrupt-context handler for the SMM interface: The SMM interface command handleroperates in interrupt context to provide a fast command response time for commands issuedby the BIOS from within the BIOS SMI Handler. For SMM-supported commands that requiresignificant processing time, the SMM command handler returns a successful completioncode for the command so the SMI handler is not delayed, while passing the command to theregular queued command handler. The command is executed in thread context but noresponse is returned to the BIOS. Commands that can be executed within the interruptcontext of the SMM command handler can potentially execute in the middle of a commandexecution by the queued task-context handler.A queued task-context handler for all other interfaces: Commands placed in the queuedtask-context command handler are executed in a first-come, first-served, single-threadedfashion. Commands that may take extra time to execute, such as FRU access commands,delay other commands until they complete.10.2 Power On / Off Issues Related to CommandsAt the command interface level, the system power on / off status does not affect the validity ofcommands. The effectiveness of the command or the interpretation of its results sometimesmust be interpreted within the context of the server’s power state:A transition of server power from off to on is the equivalent of a system reset. Settings thatare not relevant with power-off are meaningless. For example, the global-enables settingcan be set with the power off. Global enable bits controlling actions that occur only when thepower is on are reset when the power is turned on. While it is possible to change these bitswhile the power is off, doing so has no effect. A similar example exists with most sensorthresholds and event enables, which are reset when system power is applied.Most sensors are not scanned when the system is powered off. While any sensor can beread, most of the values are from the last sensor reading before the server was powered off.Threshold or event message settings are lost when power is applied, but changing thesettings with the power off could result in event messages based on the frozen sensorRevision 1.1Intel ® Confidential 85
IPMI Command InterfaceIntel® Server System "Emerald Ridge” Integrated Baseboard Management Controller EPSreading.When the system power is off, sensors that are enabled but not scanned have the sensorupdate in progress bit set in the response to Get Sensor Reading, Get Sensor Event Status, orGet Sensor Event Enable IPMI commands.10.3 BMC Command TablesThe tables on the following pages present the commands, requests, and responses that theBMC accepts from the IPMB, LPC, LAN, and Serial interfaces. Responses go out on theinterface on which the request was received.Table 34. BMC Intelligent Platform Management Interface (IPMI) CommandsNet Function = Application (06h), , LUN = 00CodeCommandRequest, Response DataDescription01h Get Device ID Per the Intelligent Platform-specific response fields:Platform Management• Byte 2 (device ID) – 21hInterface SpecificationSecond Generation • Byte 3 (device revision)v2.0• Byte 4 – Firmware revision 1Opcode firmware revision, major (binary) when Opcodefirmware is runningBoot firmware revision, major (binary) OR’ed with 0x80when Boot firmware is runningOpcode firmware revision, major (binary) OR’ed with0x80 when firmware transfer mode enteredfrom Opcode firmware.• Byte 5 – Firmware revision 2Opcode firmware revision, minor (BCD) when Opcodefirmware is running or when firmware transfermode is entered from Opcode firmwareBoot firmware revision, minor (BCD) when Bootfirmware is running.• Byte 6 (IPMI version) – 02h• Byte 7 (Additional device support)Bit 7 – Chassis deviceBit 6 – BridgeBit 5 – IPMB event generatorBit 4 – IPMB event receiverBit 3 – FRU inventory deviceBit 2 – SEL deviceBit 1 – SDR repository deviceBit 0 – Sensor device• Bytes 8:10 (manufacturer ID) – 343 (57h, 01h, 00h)• Bytes 11:12 (Emerald Ridge product ID, 40h,00h )• Bytes 13:16 (Op 109726tional auxiliary firmware revisioninformation)• Byte 13 – Boot firmware revision, major (binary)86Intel ConfidentialRevision 1.1
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