Intel® Server System Server System "Emerald Ridge ... - CTL

Intel® Server System "Emerald Ridge” ” Integrated Baseboard Management Controller EPS 錯 誤 ! 尚 未 定 義 樣 式 。With the Set BMC Global Enables command, the BMC can generate an interrupt requestingattention when setting the SMS_ATN bit in the status register.The SMS_ATN bit that is set indicates one or more of the following:There is at least one message in the BMC receive message queueAn event is in the event message buffer- Watchdog pre-timeout interrupt flag has been setAll conditions must be cleared and all BMC to SMS messages must be flushed for theSMS_ATN bit to be cleared.The host I/O address of the SMS interface is 0CA2h – 0CA3h.The operation of the SMS interface is described in the Intelligent Platform ManagementInterface Specification. See the chapter titled, “Keyboard Controller Style (KCS) Interface.”4.6.4.1 Canceling In-progress CommandsSoftware can cancel an in-progress transaction by issuing a new WRITE_START command tothe interface. However, there are cases where the BMC has accepted the command andqueued it up for execution. In these cases, the commands are executed even if the transactionhas been canceled.Since the SMS interface is single-threaded, the BMC does not accept a new command until thecurrent, canceled-in-progress command has completed execution. Until then, any newcommand sent via the SMS interface is responded to with a NODE_BUSY completion code.When the current, canceled-in-progress command is complete, the BMC discards the responseand the SMS interface accepts commands for execution.4.6.5 SMM InterfaceThe SMM interface is a KCS interface that is used by the BIOS when interface response time isa concern, for example with the BIOS SMI handler. The BMC gives this interface priority overother communication interfaces. The BMC has limits on how many back-to-back transactions itcan handle without loss in responsiveness. It must be able to handle up to 30 back-to-backcommands from the BIOS.The BMC implements the optional Get Status / Abort transaction on this interface. Only LUN 1 issupported on this interface. In addition, the status register OEM1/2 bits are defined as specifiedin Section 4.6.3.The event message buffer is shared across SMS and SMM interfaces.The host I/O address of the SMM interface is 0CA4h – 0CA5h.4.7 IPMB Communication InterfaceThe IPMB communication interface uses the 100 KB/s version of an I 2 C bus as its physicalmedium. For more information on I 2 C specifications, see The I 2 C Bus and How to Use It. TheIPMB implementation in the BMC is compliant with the IPMB v1.0, revision 1.0.Revision 1.1Intel ® Confidential 61