Intel® Server System Server System "Emerald Ridge ... - CTL

錯 誤 ! 尚 未 定 義 樣 式 。錯 誤 ! 尚 未 定 義 樣 式 。 EPS3.23 Memory Hot Plug and Memory Offline/OnlineEmerald Ridge supports memory RAS features for memory hot-plug and on-lining/off-liningoperations.The memory hot-plug feature allows the end user to remove and/or insert memory boards whilethe system continues to run. Only a single memory board may be removed or inserted at a time.Memory Hot Plug is supported by the system BIOS and the BMC FW does not directlyparticipate, however there are interactions with the BMC’s polling of the DIMM temperaturesensors and Mill Brook temperature sensors, as described below.BIOS must utilize the appropriate SPD SMBus segment to access the DIMM SPD EEPROM aspart of the hot-plug/on-line/off-line operation. The BMC uses these same SPD SMBus segmentsfor polling of the DIMM and Memory Buffer temperature sensors. Since memory-hot plug andmemory on-lining can take place at any time.Additionally, just as it does during POST, when new memory is added or brought online; BIOSmust configure the DIMM temperature sensors appropriately and provide the BMC with the newDIMM population status as well as notification that the configuration has completed.When the memory hot-plug is initiated, DIMM and Memory Buffer temperature sensors are nolonger available to the BMC FW and the fan control algorithms will apply a default fan speed tofan zones controlled by these sensors. As the hot-plug operation completes, BIOS will updatethe BMC with new memory device and Memory Buffer population data and the BMC will regainaccess to the Sensors. Semaphore OperationTo facilitate sharing of these SMBus segments, semaphores are supported (one semaphore perSMBus segments attached to each CPU). In normal operational flow during runtime, ownershipof a semaphore is requested from the BMC by BIOS by use of an IPMI OEM command.However, in case the BMC is not responsive or otherwise does not give up the bus in a timelymanner, BIOS may forcibly take over the bus.The semaphores are instantiated in the form of 4 bits in one of the IBMC’s mailbox registers,which can be set or cleared by both the BMC and BIOS. The usage of these bits is defined asfollows:• A 0 indicates that BIOS owns the bus and a 1 indicates that the BMC owns the bus.• At AC power-on, the default state of these mailbox register bits is 0.• BIOS is the default owner of the all the busses once a reset has occurred until POSTcompletes. At the start of POST, BIOS clears all the semaphore bits (= BIOS ownership).Before POST completes, BIOS sets all the semaphore bits (= BMC ownership).• During runtime, if BIOS needs bus ownership, it must first try to acquire the busownership through the IPMI OEM command method. Only if the BMC doesn’t give upthe bus after a timeout and retry by BIOS, then BIOS may forcibly take over the bus byclearing the associated semaphore bit.38Intel ConfidentialRevision 1.1