Intel® Server System Server System "Emerald Ridge ... - CTL

Intel® Server System "Emerald Ridge” Integrated Baseboard Management Controller EPSGlossaryGlossaryTermACPIAESAMBAPICARPASFASICBISTBMCBridgeBSPCBCCLICLTTCMOSCSRD-cacheDHCPDIBDPCEEPROMEMPEPSFMLFNIFRBFRUFSBFTMGPIOHSBPHSCI-cacheI2CIAIBFICHIERRINITDefinitionAdvanced Configuration and Power InterfaceAdvanced Encryption StandardAdvanced Memory Buffer (there is an AMB on each FBDIMM)Advanced Programmable Interrupt ControllerAddress Resolution ProtocolAlert Standards ForumApplication specific integrated circuitBuilt-in self testBaseboard management controllerCircuitry connecting one computer bus to another, allowing an agent on one to access the other.Bootstrap processorChassis bridge controller. A microcontroller connected to one or more other CBCs. Together theybridge the IPMB buses of multiple chassis.Command-line interfaceClosed-loop thermal throttling (memory throttling mode)In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytesof memory on the server board.Control and status registerData cache. Processor-local cache dedicated for memory locations explicitly loaded and stored byrunning code.Dynamic Host Configuration ProtocolDevice Information BlockDirect Platform ControlElectrically erasable programmable read-only memoryEmergency management portExternal Product SpecificationFast management linkFast management link network interfaceFault resilient bootingField replaceable unitFront side busFirmware transfer modeGeneral-purpose input/outputHot-swap backplaneHot-swap controllerInstruction cache. Processor-local cache dedicated for memory locations retrieved through instructionfetch operations.Inter-integrated circuit busIntel ® architectureInput bufferI/O controller hubInternal errorInitialization signalRevision 1.0Intel ® Confidential 177