Intel® Server System Server System "Emerald Ridge ... - CTL

錯 誤 ! 尚 未 定 義 樣 式 。 EPSFunctional Specification3.21 Power Throttle SensorThe BMC supports a PLD Power Throttle sensor which is used to log a SEL event whenmemory controller and/or the CPUs are throttled encountering an over power drawn conditionfor the given power supply configuration and capabilities. When power supply utilization is morethan 80% of throttling limits, PDB FW will notify the PLD immediately and PLD FW will decidethe system need throttle memory controller and/or the CPUs or not. Moreover the throttlinglimits are established by the PDB controller based on the number of PSU installed and notbased on the FRUSDR setup of the power supply configuration. The power supply redundancyconfiguration in FRUSDR setup only influenced the SEL and the system status LED.System will throttle Memory controller when• All 4x power supplies are not installed in the system OR multiple power supplies failedeven though all 4x power supplies are installed (Don’t assert this signal with three ormore functional power supplies).AND• Memory VR current trip point (default setting: 90% of supported TDP current) is triggered.AND• System power utilization is high and exceeds a pre-set limit of 80%.System will throttle CPU when• All 4x power supplies are not installed in the system OR multiple power supplies failedeven though all 4x power supplies are installed (Don’t assert this signal with three ormore functional power supplies).AND• Processor VR current trip point (default setting: 90% of supported TDP current) istriggered.AND• System power utilization is high and exceeds a pre-set limit of 80%.BMC monitors throttling of CPU and Memory Controller and logs an SEL event. Power throttlesensor is implemented as manual rearm sensor.Upon assertion of the sensor offset, BMC starts an internal time of 30 mins. BMC will re-arm thesensor when the timer expires. The sensor is also re-armed when the system is reset or DCpower-cycled.3.22 Memory Riser Power Failure MonitoringThe BMC supports detection of memory riser power failures. As soon as power failure happensin any of memory riser/s, PLD detects power failures and powers down the server. BMC readsthe PLD status bits to find out location of failed memory riser and logs assertion event forMemory Riser Power Fail sensor assertion offset. BMC implements eight memory riser powerfailure sensors one for each memory riser, These sensors are readable in DC off state as well,so that users can see if these sensors are asserted by any of memory board failure. Memoryriser power failure sensors are implemented as auto-rearm sensors. Once the event is assertedby BMC due to failed memory riser, it would be de-asserted during DC reset.Revision 1.1Intel ® Confidential 37