IntelÃ‚Â® Server System Server System "Emerald Ridge ... - CTL

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錯誤 ! 尚未定義樣式。 EPSFunctional Specification3. Functional Specifications3.1 Power <strong>System</strong>The BMC is in-line with the system power control path. This is implemented by an integratedhardware signal pass-through. The pass-through allows the BMC to directly block power-on ifnecessary. If the BMC firmware is non-functional, the default state of the pass-through hardwareis to allow full system control. This is to provide a means of power control in case a BMCfirmware recovery is necessary.The following block diagram shows the power and reset signal interconnections to the BMC.The signals names and interconnections may not match the names in schematics. These arechosen to illustrate functional descriptions provided in this document.Figure 2. BMC Power / Reset SignalsRevision 1.1Intel ® Confidential 7
錯誤 ! 尚未定義樣式。錯誤 ! 尚未定義樣式。 EPS3.1.1 Power Supply Interface SignalsThe BMC controls the POWER_ON signal. It connects to the chassis power sub-system and isused to request power state changes (asserted = request power on). The PS_PWRGD signalfrom the chassis power sub-system indicates the current power state (asserted = power is on).Figure 2 shows the power supply control signals and their sources. To turn the system on, theBMC asserts the PS_ON signal and waits for the PS_PWRGD signal to assert in response,indicating that DC power is on.The PS_PWRGD signal is normally asserted within 1.5 seconds, but the timeout interval can beset longer to add flexibility in manufacturing test environments. The POWER_GOOD signalmust remain stable and not glitch when being asserted. The BMC uses the state of thePS_PWRGD signal to monitor whether the power supply is on and operational, and to confirmwhether the system power state matches the intended system on / off power state that wascommanded with the PS_ON signal.3.1.2 Power-Good DropoutDe-assertion of the PS_PWRGD signal generates an interrupt that the BMC uses to detecteither power sub-system failure or loss of AC power. A power-good dropout is defined as thePS_PWRGD signal de-asserting when the system should be in the DC power-on state asdetermined by the state of the PS_ON signal. The PS_PWRGD deassertion must also coincidewith the assertion of the “CPU Power Failure Status” bit in the chipset. Note that BIOS must deassertthe “CPU Power Failure Status” bit on a normal power-on.If the BMC detects a power-good dropout, the following occurs:1. Hardware powers down the system.2. The BMC asserts the Power Unit Failure offset of the Power Unit sensor and logs a SELevent. See Section 3.28.1.4.3. The BMC generates a beep code for a Power Fault. See Table 8.The BMC waits 10 seconds. If the power state retention feature is configured to poweron the server after an AC loss, it attempts to power up the server.The BMC responds to the power loss interrupt within 1-2 ms if it is in operational mode.3.1.3 Power-up SequenceTo power up the system, the BMC simulates the front panel power button press by disabling thepower button pass-through mode temporary, generating a 200 ms pulse of the power buttonsignal (Pilot II internally triggers a 100 ms pulse on each valid wakeup event; we double thelength for the button press signals), and checking the PS_PWRGD assertion. If thePS_PWRGD is not asserted, it waits for a second before retrying the power-up sequence againfor a maximum of eight retries, with a total duration of approximately 9.6 seconds. If thePS_PWRGD is still not asserted at the end of the eight retries, a fault is generated.After simulating the front panel power button press, the BMC initializes all sensors to theirpower-on initialization state. The initialization agent is run. The firmware handles this sequence.8Intel ConfidentialRevision 1.1
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IntelÃ‚Â® Server System Server System "Emerald Ridge ... - CTL

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