Intel® Server System Server System "Emerald Ridge ... - CTL

錯 誤 ! 尚 未 定 義 樣 式 。 EPSFunctional Specification3.1.4 Power Down SequenceTo power down the system, the BMC simulates the front panel power button press by disablingthe power button pass-through mode, generating a 200 ms pulse of the power button signal,and checking the PS_PWRGD drop. If the PS_PWRGD does not drop as expected, it waits fora second before sending another 200 ms pulse of the power button signal for a maximum ofeight retries. After the eight retires, if the PS_PWRGD is still asserted, the BMC will force thesimulation of the power button 4-second override mode. This guarantees that the system will bepowered off after the failure of eight power-down retries. A fault is not generated.Before initiating the system power down, the BMC stops scanning any sensors that should notbe scanned in the powered-down state.To power cycle the system via the IPMI command, the BMC simulates the front panel powerbutton to (1) power down the system, (2) wait for a second, and then (3) power up the system.Similar to the power-up sequence, if the BMC failed to power down the system, it takes controlby changing the ONCTLn signal. After a 5-second wait, the BMC gives control back to theexternal APCI logic. The system will be powered up by the SLPS3n/SLPS5n signals. Thefirmware handles this sequence.3.1.5 Power Control SourcesThe following sources can initiate power-up and / or power-down activity.Table 2. Power Control InitiatorsSourceExternal Signal Name orInternal Sub-systemCapabilitiesabilitiesPower button Front panel power button Turns power on or offBMC watchdog timer Internal BMC timer Turns power off, or power cycleCommand Routed through command processor Turns power on or off, or power cyclePower state retention Implemented via BMC internal logic Turns power on when AC power returnsChipsetSleep S4 / S5 signal (same asPOWER_ON)Turns power on or offCPU Thermal CPU Thermtrip Turns power off3.1.5.1 Power Button SignalThe POWER_BUTTON signal is filtered through a 16 ms hardware debounce. The signal mustbe in a constant state for more than 16 ms before it is treated as asserted.The signal is routed to the chipset power button signal through pass-through and SIO circuitrythat allows the BMC to lock out the signal. The chipset responds to the assertion of the signal; itreacts to the press of the button, not the release of it.3.1.5.2 Chipset Sleep S4 / S5The BMC is notified of S4/S5 transitions by the BIOS, through the SMM interface.Revision 1.1Intel ® Confidential 9