Intel® Server System Server System "Emerald Ridge ... - CTL

錯 誤 ! 尚 未 定 義 樣 式 。Intel® Server System "Emerald Ridge” Integrated Baseboard Management Controller EPS4.6.3 SMS / SMM Status RegisterBits in the status register provide interface and protocol state information. As an extension to theIPMI 2.0 KCS interface definition, the OEM1 and OEM2 bits in the SMS and SMM interfaceshave been defined to provide BMC status information. Table 28 summarizes the functions of thestatus register bits. Read/write is from the perspective of the host interface. All status registerbits are read-only to the host.BitName7 S16 S05 BMC State1 (OEM2)4 BMC State0 (OEM1)Table 28. SMS / SMM Status Register BitsDescriptionBits 7 and 6 indicate the current state of this KCS interface. The host software examinesthese bits to verify that they are in sync with the BMC. For more information on these bits,refer to the Intelligent Platform Management Interface Specification Second Generationv2.0.These bits provide a status indication of BMC health:00b – BMC ready01b – BMC hardware error (i.e., BMC memory test error)10b – BMC firmware checksum error11b – BMC is not ready3 C/D# Bit 3 specifies whether the last write was to the command register or the Data_In register(1=command, 0=data). It is set by hardware to indicate whether last write from the hostwas to command or Data_In register.2 SMS_ATN /SMM_ATNWhen the status register is used for an SMS interface, the SMS_ATN bit indicates thatthe BMC has a message for the SMS.When the status register is used for an SMM interface, the SMM_ATN bit indicates thatthe BMC has a message for the SMI handler.Set this bit to 1 when the BMC has a message for the SMS / SMI handler.See Sub-sections 4.6.4 and 4.6.5 for more details on these flag bits.1 IBF Input buffer is full. Set this bit to 1 when either the associated command or Data_Inregister has been written by system-side software. Cleared to 0 by the BMC reading thedata register.0 OBF Output buffer is full. Set this bit to 1 when the associated Data_Out register is written bythe BMC. Cleared to 0 by the host reading the data register.Note: When the BMC is reset from either a power-on or a hard reset, the protocol state bits(S0,S1) are initialized to 11b–Error State and the BMC state bits (BMC State 0/1) are initializedto 00b – BMC Ready. This allows host software to detect that the BMC has been reset and thatthe BMC has terminated any in-process messages.The BMC state bits are set to 11b – BMC not ready if the BMC is busy; such as during SEL orSDR erasure or while the Initialization Agent is running.4.6.4 Server Management Software (SMS) InterfaceThe SMS interface is the BMC host interface. The BMC implements the SMS KCS interface asdescribed in the Intelligent Platform Management Interface Specification Second Generationv2.0. The BMC implements the optional Get Status / Abort transaction on this interface. Onlylogical unit number (LUN) 0 is supported on this interface. The status register OEM1/2 bits arecovered in Section 4.6.3.60Intel ConfidentialRevision 1.1